4.3.59. L2 Extended Control Register, EL1

The L2ECTLR_EL1 characteristics are:

Purpose

Provides additional implementation defined control options for the L2 memory system. There is one L2 Extended Control Register for the Cortex-A57 MPCore device.

Usage constraints

The accessibility to the L2ECTLR_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RW[a]RW[a]RW[b]RWRW

[a] Write access if ACTLR_EL3.L2ECTLR is 1 and ACTLR_EL2.L2ECTLR is 1, or ACTLR_EL3.L2ECTLR is 1 and the Secure SCR.NS is 0.

[b] Write access if ACTLR_EL3.L2ECTLR is 1.

The L2ECTLR_EL1 can be written dynamically.

Configurations

The L2ECTLR_EL1 is:

  • Common to the Secure and Non-secure states.

  • A 32-bit register in AArch64 state.

  • Architecturally mapped to the AArch32 L2ECTLR register.

Attributes

See the register summary in Table 4.15.

Figure 4.51 shows the L2ECTLR bit assignments.

Figure 4.51. L2ECTLR_EL1 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.68 shows the L2ECTLR_EL1 bit assignments.

Table 4.68. L2ECTLR_EL1 bit assignments

BitsNameFunction
[31]-

Reserved, res0.

[30]L2 internal asynchronous error

L2 internal asynchronous error caused by L2 RAM double-bit ECC error. The possible values are:

0

No pending asynchronous error. This is the reset value.

1

An asynchronous error has occurred.

A write of 0 clears this bit. A write of 1 is ignored.

[29]AXI or CHI asynchronous error

AXI or CHI asynchronous error indication. The possible values are:

0

No pending asynchronous error. This is the reset value.

1

An asynchronous error has occurred.

A write of 0 clears this bit. A write of 1 is ignored.

[28:3]-

Reserved, res0.

[2:0]

L2 dynamic retention control

L2 dynamic retention control. The possible values are:

0b000

L2 dynamic retention disabled. This is the reset value.

0b001

2 Generic Timer ticks required before retention entry.

0b010

8 Generic Timer ticks required before retention entry.

0b011

32 Generic Timer ticks required before retention entry.

0b100

64 Generic Timer ticks required before retention entry.

0b101

128 Generic Timer ticks required before retention entry.

0b110

256 Generic Timer ticks required before retention entry.

0b111

512 Generic Timer ticks required before retention entry.

See L2 RAMs dynamic retention for more information.


To access the L2ECTLR_EL1 in AArch32 state, read or write the CP15 register with:

MRS <Xt>, S3_1_c11_c0_3; Read L2 Extended Control Register
MSR S3_1_c11_c0_3, <Xt>; Write L2 Extended Control Register

To access the L2ECTLR in AArch32 state, read or write the CP15 register with:

MRC p15, 1, <Rt>, c9, c0, 3; Read L2 Extended Control Register
MCR p15, 1, <Rt>, c9, c0, 3; Write L2 Extended Control Register
Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914