4.3.40. Architectural Feature Trap Register, EL3

The CPTR_EL3 characteristics are:

Purpose

Controls trapping to EL3 for accesses to the CPACR_EL1 register, trace functionality and registers associated with floating-point and SIMD execution. Also controls EL3 access to this functionality.

Usage constraints

The accessibility of the CPTR_EL3 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
----RWRW
Configurations

The CPTR_EL3 is a 32-bit register.

Attributes

See the register summary in Table 4.12.

Figure 4.36 shows the CPTR_EL3 bit assignments.

Figure 4.36. CPTR_EL3 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.52 shows the CPTR_EL3 bit assignments.

Table 4.52.  CPTR_EL3 bit assignments

BitsNameFunction
[63:32]-

Reserved, res0.

[31]TCPAC

Traps direct access to CPACR_EL1 from EL1 to EL3. The possible values are:

0

Access to CPACR_EL1 is not trapped. This is the reset value.

1

Access to CPACR_EL1 is trapped.

[30:21]-

Reserved, res0.

[20]TTAThis bit is res0. The processor does not support System register access to trace functionality.
[19:11]-

Reserved, res0.

[10]TFP

Traps instructions that access registers associated with floating-point and Advanced SIMD execution from a lower Exception level to EL3, unless trapped to EL1. The possible values are:

0

Instructions that access registers associated with floating-point and Advanced SIMD execution are not trapped.

1

Instructions that access registers associated with floating-point and Advanced SIMD execution are trapped. This is the reset value.

[9:0]-

Reserved, res0.


To access the CPTR_EL3 in AArch64 state, read or write the register with:

MRS <Xt>, CPTR_EL3; Read EL3 Architectural Feature Trap Register
MSR CPTR_EL3, <Xt>; Write EL3 Architectural Feature Trap Register
Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914