4.2.2. AArch64 exception handling registers

Table 4.2 shows the fault handling registers in AArch64 state. Bits[63:32] are reset to 0x00000000 for all 64-bit registers in Table 4.2.

Table 4.2. AArch64 exception handling registers

AFSR0_EL1RWres032Auxiliary Fault Status Register 0, EL1 and EL3
AFSR1_EL1RWres032Auxiliary Fault Status Register 1, EL1 and EL3

Exception Syndrome Register, EL1 and EL3

IFSR32_EL2RWUNK32Instruction Fault Status Register, EL2
AFSR0_EL2RWres032Auxiliary Fault Status Register 0, EL2 and Hyp Auxiliary Data Fault Status Register
AFSR1_EL2RWres032Auxiliary Fault Status Register 1, EL2 and Hyp Auxiliary Instruction Fault Status Register
ESR_EL2RWUNK32Exception Syndrome Register, EL2
AFSR0_EL3RWres032Auxiliary Fault Status Register 0, EL1 and EL3
AFSR1_EL3RWres032Auxiliary Fault Status Register 1, EL1 and EL3
ESR_EL3RWUNK32Exception Syndrome Register, EL1 and EL3

Fault Address Register, EL1 [a]

FAR_EL2RWUNK64Fault Address Register, EL2 [a]

Hyp IPA Fault Address Register, EL2 [a]

FAR_EL3RWUNK64Fault Address Register, EL3 [a]

Vector Base Address Register, EL1 [a]


Interrupt Status Register [a]


Vector Base Address Register, EL2 [a]

[a] See the ARM® Architecture Reference Manual ARMv8 for more information.

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