4.4.22. Cache maintenance operations

Table 4.103 shows the System instructions for cache and branch predictor maintenance operations in AArch32 state. See the ARM® Architecture Reference Manual ARMv8 for more information about these operations.

Table 4.103. Cache and branch predictor maintenance operations

NameCRnop1CRmop2Description
ICIALLUISc70c10

Instruction Cache invalidate all to PoU[a] Inner Shareable

BPIALLIS  6

Branch predictor invalidate all Inner Shareable

ICIALLU  c50

Instruction Cache invalidate all to PoU

ICIMVAU  1

Instruction Cache invalidate by VA to PoU

BPIALL  6

Branch predictor invalidate all

BPIMVA  7

Branch predictor invalidate by VA

DCIMVAC  c61

Data cache invalidate by VA to PoC[b]

DCISW  2

Data cache invalidate by set/way

DCCMVAC  c101

Data cache clean by VA to PoC

DCCSW  2

Data cache clean by set/way

DCCMVAU  c111

Data cache clean by VA to PoU

DCCIMVAC  c141

Data cache clean and invalidate by VA to PoC

DCCISW  2

Data cache clean and invalidate by set/way

[a] PoU = Point of Unification. PoU is set by the BROADCASTINNER signal and can be in the L1 data cache or outside of the processor, in which case PoU is dependent on the external memory system.

[b] PoC = Point of Coherence. The PoC is always outside of the processor and is dependent on the external memory system.


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