4.4.24. Address translation operations

Table 4.105 shows the address translation register in AArch32 state.

Table 4.105. Address translation register

NameCRnop1CRmop2ResetWidthDescription
PARc70c40UNK32-bitPhysical Address Register
-0c7-64-bit

Table 4.105 shows the System instructions for address translation operations in AArch32 state.

Table 4.106. Address translation operations

NameCRnop1CRmop2ResetWidthDescription
ATS1CPRc70c80UNK32-bit

Stage 1 current state EL1 read [a]

ATS1CPW  1UNK32-bit

Stage 1 current state EL1 write [a]

ATS1CUR  2UNK32-bit

Stage 1 current state unprivileged read [a]

ATS1CUW  3UNK32-bit

Stage 1 current state unprivileged write [a]

ATS12NSOPR  4UNK32-bit

Stages 1 and 2 Non-secure EL1 read [a]

ATS12NSOPW  5UNK32-bit

Stages 1 and 2 Non-secure EL1 write [a]

ATS12NSOUR  6UNK32-bit

Stages 1 and 2 Non-secure unprivileged read [a]

ATS12NSOUW  7UNK32-bit

Stages 1 and 2 Non-secure unprivileged write [a]

ATS1HR 4c80UNK32-bit

Stage 1 Hyp mode read [a]

ATS1HW  1UNK32-bit

Stage 1 Hyp mode write [a]

[a] See the ARM® Architecture Reference Manual ARMv8 for more information.


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