ARM Cortex-A57 MPCore Processor Technical Reference Manual: 4.4.24. Address translation operations

Table 4.105 shows the address translation register in AArch32 state.

Table 4.105. Address translation register

Name	CRn	op1	CRm	op2	Reset	Width	Description
PAR	c7	0	c4	0	UNK	32-bit	Physical Address Register
PAR	-	0	c7	-	UNK	64-bit	Physical Address Register

Table 4.105 shows the System instructions for address translation operations in AArch32 state.

Table 4.106. Address translation operations

Name	CRn	op1	CRm	op2	Reset	Width	Description
`ATS1CPR`	c7	0	c8	0	UNK	32-bit	Stage 1 current state EL1 read ^[a]
`ATS1CPW`				1	UNK	32-bit	Stage 1 current state EL1 write ^[a]
`ATS1CUR`				2	UNK	32-bit	Stage 1 current state unprivileged read ^[a]
`ATS1CUW`				3	UNK	32-bit	Stage 1 current state unprivileged write ^[a]
`ATS12NSOPR`				4	UNK	32-bit	Stages 1 and 2 Non-secure EL1 read ^[a]
`ATS12NSOPW`				5	UNK	32-bit	Stages 1 and 2 Non-secure EL1 write ^[a]
`ATS12NSOUR`				6	UNK	32-bit	Stages 1 and 2 Non-secure unprivileged read ^[a]
`ATS12NSOUW`				7	UNK	32-bit	Stages 1 and 2 Non-secure unprivileged write ^[a]
`ATS1HR`		4	c8	0	UNK	32-bit	Stage 1 Hyp mode read ^[a]
`ATS1HW`			c8	1	UNK	32-bit	Stage 1 Hyp mode write ^[a]
^[a]See the ARM^® Architecture Reference Manual ARMv8 for more information.

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