4.5.11. Hyp Configuration Register 2

The HCR2 characteristics are:

Purpose

Provides additional configuration controls for virtualization.

Usage constraints

The accessibility to the HCR2 in AArch32 state by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
---RWRW-
Configurations

The HCR2 is:

Attributes

See the register summary in Table 4.83.

Figure 4.88 shows the HCR2 bit assignments.

Figure 4.88. HCR2 bit assignments

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Table 4.122 shows the HCR2 bit assignments.

Table 4.122. HCR2 bit assignments

BitsNameFunction
[31:2]-

Reserved, res0.

[1]ID

Stage 2 Instruction Cache disable. When HCR_EL2.VM is 1, this forces all stage2 translations for instruction accesses to Normal memory to be Non-cacheable for the EL1/EL0 translation regime. The values are:

0

No effect on the stage 2 of the EL1/EL0 translation regime for instruction accesses. This is the reset value.

1

Forces all stage 2 translations for instruction accesses to Normal memory to be Non-cacheable for the EL0/EL1 translation regime.

[0]CD

Stage 2 Data cache disable. When HCR_EL2.VM is 1, this forces all stage2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable for the EL1/EL0 translation regime. The values are:

0

No effect on the stage 2 of the EL1/EL0 translation regime for data accesses and translation table walks. This is the reset value.

1

Forces all stage 2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable for the EL0/EL1 translation regime.


To access the HCR2 in AArch32 state, read or write the CP15 register with:

MRC p15, 4, <Rt>, c1, c1, 4; Read Hyp Configuration Register 2
MCR p15, 4, <Rt>, c1, c1, 4; Write Configuration Register 2
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