4.3.33. Auxiliary Control Register, EL2

The ACTLR_EL2 characteristics are:

Purpose

Controls access to implementation defined registers in Non-secure EL1.

Usage constraints

The accessibility to ACTLR_EL2 in AArch64 state by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
---RWRWRW

The accessibility to the HACTLR in AArch32 state by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
---RWRW-
Configurations

The ACTLR_EL2 is:

  • A Banked EL2 register.

  • Architecturally mapped to the AArch32 HACTLR register.

Attributes

See the register summary in Table 4.4.

Figure 4.30 shows the ACTLR_EL2 bit assignments.

Figure 4.30. ACTLR_EL2 bit assignments

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Table 4.46 shows the ACTLR_EL2 bit assignments.

Table 4.46. ACTLR_EL2 bit assignments

BitsNameFunction
[31:7]-

Reserved, res0.

[6]L2ACTLR access control

L2ACTLR access control. The possible values are:

0

The register is not accessible from Non-secure EL1.

1

The register is accessible from Non-secure EL1.

[5]L2ECTLR access control

L2ECTLR access control. The possible values are:

0

The register is not accessible from Non-secure EL1.

1

The register is accessible from Non-secure EL1.

[4]L2CTLR access control

L2CTLR access control. The possible values are:

0

The register is not accessible from Non-secure EL1.

1

The register is accessible from Non-secure EL1.

[3:2]-

Reserved, res0.

[1]CPUECTLR access control

CPUECTLR access control. The possible values are:

0

The register is not accessible from Non-secure EL1.

1

The register is accessible from Non-secure EL1.

[0]CPUACTLR access control

CPUACTLR access control. The possible values are:

0

The register is not accessible from Non-secure EL1.

1

The register is accessible from Non-secure EL1.


To access the ACTLR_EL2 in AArch64 state, read or write the register with:

MRS <Xt>, ACTLR_EL2; Read EL2 Auxiliary Control Register
MSR ACTLR_EL2, <Xt>; Write EL2 Auxiliary Control Register

To access the HACTLR in AArch32 state, read or write the CP15 register with:

MRC p15, 4, <Rt>, c1, c0, 1; Read Hypervisor Auxiliary Control Register
MCR p15, 4, <Rt>, c1, c0, 1; Write Hypervisor Auxiliary Control Register
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