4.3.28. Virtualization Processor ID Register, EL2

The VPIDR_EL2 characteristics are:

Purpose

Holds the value of the Virtualization Processor ID. A Non-secure read of the MIDR from EL1 returns the value of this register. See Table 4.16.

Usage constraints

The accessibility to the VPIDR_EL2 in AArch64 state by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
---RWRWRW

The accessibility to the VPIDR in AArch32 state by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
---RWRW-
Configurations

The VPIDR_EL2 is:

  • A Banked EL2 register.

  • Architecturally mapped to the AArch32 VPIDR register.

Attributes

See the register summary in Table 4.13.

Figure 4.26 shows the VPIDR_EL2 bit assignments.

Figure 4.26. VPIDR_EL2 bit assignments

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Table 4.42 shows the VPIDR_EL2 bit assignments.

Table 4.42. VPIDR_EL2 bit assignments

BitsNameFunction
[31:0]VPIDR

MIDR value returned by Non-secure EL1 reads of the MIDR. For information on the subdivision of this value, see Table 4.16.


To access the VPIDR_EL2 in AArch64 state, read or write the register with:

MRS <Xt>, VPIDR_EL1; Read Virtualization Processor ID Register
MSR VPIDR_EL1, <Xt>; Write Virtualization Processor ID Register

To access the VPIDR, read or write the CP15 register with:

MRC p15, 4, <Rt>, c0, c0, 0; Read Virtualization Processor ID Register
MCR p15, 4, <Rt>, c0, c0, 0; Write Virtualization Processor ID Register
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