4.2.3. AArch64 virtual memory control registers

Table 4.3 shows the virtual memory control registers in AArch64 state. Bits[63:32] are reset to 0x00000000 for all 64-bit registers in Table 4.3.

Table 4.3. AArch64 virtual memory control registers

NameTypeResetWidthDescription
SCTLR_EL1RW0x00C50838[a]32

System Control Register, EL1

SCTLR_EL2RW0x30C5083832

System Control Register, EL2 [b]

SCTLR_EL3RW0x00C50838 [a]32System Control Register, EL3
TTBR0_EL1RWUNK64

Translation Table Base Address Register 0, EL1 [b]

TTBR1_EL1RWUNK64Translation Table Base Address Register 1, EL1 [b]
TCR_EL1RWUNK64Translation Control Register, EL1
TTBR0_EL2RWUNK64Translation Table Base Address Register 0, EL2 [b]
TCR_EL2RWUNK32Translation Control Register, EL2
VTTBR_EL2RWUNK64

Virtualization Translation Table Base Address Register, EL2 [b]

VTCR_EL2RWUNK32Virtualization Translation Control Register, EL2
TTBR0_EL3RWUNK64

Translation Table Base Address Register 0, EL3 [b]

TCR_EL3RWUNK32Translation Control Register, EL3
MAIR_EL1RWUNK64

Memory Attribute Indirection Register, EL1 [b]

AMAIR_EL1RWres064Auxiliary Memory Attribute Indirection Register, EL1 and EL3
MAIR_EL2RWUNK64

Memory Attribute Indirection Register, EL2 [b]

AMAIR_EL2RWres064Auxiliary Memory Attribute Indirection Register, EL2
MAIR_EL3RWUNK64

Memory Attribute Indirection Register, EL3 [b]

AMAIR_EL3RWres064Auxiliary Memory Attribute Indirection Register, EL1 and EL3
CONTEXTIDR_EL1RWUNK32

Context ID Register, EL1 [b]

[a] The reset value depends on primary input CFGTE. Table 4.3 assumes this signal is LOW.

[b] See the ARM® Architecture Reference Manual ARMv8 for more information.


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