4.2.9. AArch64 Performance Monitors registers

Table 4.10 shows the Performance Monitors registers in AArch64 state. Bits[63:32] are reset to 0x00000000 for all 64-bit registers in Table 4.10.

Table 4.10. AArch64 Performance Monitors registers

NameTypeResetWidthDescription
PMCR_EL0RW [a]0x4101300032

Performance Monitors Control Register, EL0

PMCNTENSET_EL0RWUNK32Performance Monitors Count Enable Set Register [b]
PMCNTENCLR_EL0RWUNK32Performance Monitors Enable Count Clear Register [b]
PMOVSCLR_EL0RWUNK32

Performance Monitors Overflow Flag Status Register [b]

PMSWINC_EL0WO-32

Performance Monitors Software Increment Register [b]

PMSELR_EL0RWUNK32

Performance Monitors Event Counter Selection Register [b]

PMCEID0_EL0RO0x7FFF0F3F32

Performance Monitors Common Event Identification Register 0, EL0

PMCEID1_EL0RO0x0000000032Performance Monitors Common Event Identification Register 1 [b]
PMCCNTR_EL0RWUNK64

Performance Monitors Cycle Count Register [b]

PMXEVTYPER_EL0RWUNK32

Performance Monitors Selected Event Type Register [b]

PMCCFILTR_EL0RW0x0000000032Performance Monitors Cycle Count Filter Register [b]
PMXEVCNTR_EL0RWUNK32

Performance Monitors Selected Event Count Register [b]

PMUSERENR_EL0RW0x0000000032

Performance Monitors User Enable Register [b]

PMINTENSET_EL1RWUNK32Performance Monitors Interrupt Enable Set Register [b]
PMINTENCLR_EL1RWUNK32Performance Monitors Interrupt Enable Clear Register [b]
PMOVSSET_EL0RWUNK32

Performance Monitors Overflow Flag Status Set Register [b]

[a] Access permissions also depend on the access condition. See External register access permissions.

[b] See the ARM® Architecture Reference Manual ARMv8 for more information.


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