4.2.15. AArch64 implementation defined registers

Table 4.15 shows the implementation defined registers in AArch64 state. These registers provide test features and any required configuration options specific to the Cortex-A57 MPCore multiprocessor. If a register is not indicated as mapped to an AArch32 64-bit register, bits[63:32] are 0x00000000.

Table 4.15. AArch64 implementation defined registers

NameTypeResetWidthDescription
ACTLR_EL1RWres032

Auxiliary Control Register, EL1

ACTLR_EL2RW0x0000000032Auxiliary Control Register, EL2
ACTLR_EL3RW0x0000000032Auxiliary Control Register, EL3
AFSR0_EL1RWres032Auxiliary Fault Status Register 0, EL1 and EL3
AFSR1_EL1RWres032Auxiliary Fault Status Register 1, EL1 and EL3
AFSR0_EL2RWres032Auxiliary Fault Status Register 0, EL2 and Hyp Auxiliary Data Fault Status Register
AFSR1_EL2RWres032Auxiliary Fault Status Register 1, EL2 and Hyp Auxiliary Instruction Fault Status Register
AFSR0_EL3RWres032Auxiliary Fault Status Register 0, EL1 and EL3
AFSR1_EL3RWres032Auxiliary Fault Status Register 1, EL1 and EL3
AMAIR_EL1RWres064Auxiliary Memory Attribute Indirection Register, EL1 and EL3
AMAIR_EL2RWres064Auxiliary Memory Attribute Indirection Register, EL2
AMAIR_EL3RWres064Auxiliary Memory Attribute Indirection Register, EL2
L2CTLR_EL1RW0x00000000[a]32

L2 Control Register, EL1

L2ECTLR_EL1RW0x0000000032

L2 Extended Control Register, EL1

IL1DATA0_EL1RWUNK32

Instruction L1 Data n Register, EL1

IL1DATA1_EL1UNK
IL1DATA2_EL1UNK
IL1DATA3_EL1UNK
DL1DATA0_EL1RWUNK32

Data L1 Data n Register, EL1

DL1DATA1_EL1UNK
DL1DATA2_EL1UNK
DL1DATA3_EL1UNK
DL1DATA4_EL1UNK
RAMINDEXWO-32

RAM Index operation

L2ACTLR_EL1RW0x0000000000000010[b]32

L2 Auxiliary Control Register, EL1

CPUACTLR_EL1[c]RW0x0000 0000 0000 000064CPU Auxiliary Control Register, EL1
CPUECTLR_EL1[c]RW0x0000 001B 0000 000064CPU Extended Control Register, EL1
CPUMERRSR_EL1[c]RWUNK[d]64CPU Memory Error Syndrome Register, EL1
L2MERRSR_EL1[c]RWUNK[d]64L2 Memory Error Syndrome Register, EL1
CBAR_EL1ROUNK[e]64

Configuration Base Address Register, EL1

[a] The reset value depends on the processor implementation and the state of the L2RSTDISABLE signal.

[b] This is the reset value for an ACE interface. For a CHI interface the reset value is 0x0000000000004018.

[c] Mapped to a 64-bit AArch32 register.

[d] Bits[47:40, 39:32, 31] are reset to zero.

[e] The reset value depends on the primary input, PERIPHBASE[43:18].


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