4.4.17. Identification registers

Table 4.98 shows the Identification registers in AArch32 state.

Table 4.98. Identification registers

NameCRnop1CRmop2TypeResetDescription
MIDRc00c00RO0x411FD071Main ID Register. See Main ID Register, EL1.
CTR   1RO0x8444C004Cache Type Register. See Cache Type Register, EL0.
TCMTR   2-0x00000000TCM Type Register.
TLBTR   3RO0x00000000TLB Type Register.
MPIDR   5RO0x80000003[a]Multiprocessor Affinity Register.
REVIDR   6RO0x00000000Revision ID Register. See Revision ID Register, EL1.
MIDR   4, 7RO0x411FD071Aliases of Main ID Register, Main ID Register, EL1.
ID_PFR0  c10RO0x00000131Processor Feature Register 0. See AArch32 Processor Feature Register 0, EL1.
ID_PFR1   1RO0x00011011[b]Processor Feature Register 1. See AArch32 Processor Feature Register 1, EL1.
ID_DFR0   2RO0x03010066Debug Feature Register 0. See AArch32 Debug Feature Register 0, EL1.
ID_AFR0   3RO0x00000000Auxiliary Feature Register 0. See AArch32 Auxiliary Feature Register 0, EL1.
ID_MMFR0   4RO0x10101105Memory Model Feature Register 0. See AArch32 Memory Model Feature Register 0, EL1.
ID_MMFR1   5RO0x40000000Memory Model Feature Register 1. See AArch32 Memory Model Feature Register 1, EL1.
ID_MMFR2   6RO0x01260000Memory Model Feature Register 2. See AArch32 Memory Model Feature Register 2, EL1.
ID_MMFR3   7RO0x02102211Memory Model Feature Register 3. See AArch32 Memory Model Feature Register 3, EL1.
ID_ISAR0  c20RO0x02101110Instruction Set Attribute Register 0. See AArch32 Instruction Set Attribute Register 0, EL1.
ID_ISAR1   1RO0x13112111Instruction Set Attribute Register 1. See AArch32 Instruction Set Attribute Register 1, EL1.
ID_ISAR2   2RO0x21232042Instruction Set Attribute Register 2. See AArch32 Instruction Set Attribute Register 2, EL1.
ID_ISAR3   3RO0x01112131Instruction Set Attribute Register 3. See AArch32 Instruction Set Attribute Register 3, EL1.
ID_ISAR4   4RO0x00011142Instruction Set Attribute Register 4. See AArch32 Instruction Set Attribute Register 4, EL1.
ID_ISAR5   5RO0x00010001[c]Instruction Set Attribute Register 5. See AArch32 Instruction Set Attribute Register 5, EL1.
CCSIDR 1c00ROUNKCache Size ID Register. See Cache Size ID Register, EL1.
CLIDR   1RO0x0A200023Cache Level ID Register. See Cache Level ID Register, EL1.
AIDR   7-0x00000000Auxiliary ID Register. See Auxiliary ID Register, EL1.
CSSELR 2c00RWUNKCache Size Selection Register. See Cache Size Selection Register, EL1.
VPIDR 4c00RW-[d]Virtualization Processor ID Register. See Virtualization Processor ID Register, EL2.
VMPIDR   5RO-[e]Virtualization Multiprocessor ID Register. See Virtualization Multiprocessor ID Register.

[a] The reset value depends on the primary inputs, CLUSTERIDAFF1, and the number of processors that the MPCore device implements. The value shown is for a four processor implementation, with CLUSTERIDAFF1 set to zero.

[b] The reset value depends on the primary input GICCDISABLE. The value shown assumes the GICCDISABLE signal is tied HIGH.

[c] The reset value is 0x00011121 if the Cryptography engine is implemented.

[d] The reset value is the value of the Main ID Register. See Main ID Register, EL1 for more information.

[e] The reset value is the value of the Multiprocessor Affinity Register.


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