4.3.63. Data L1 Data n Register, EL1

The DL1DATAn_EL1, where n is from 0 to 4, characteristics are:

Purpose

Holds the data side L1 or L2 array information returned by the RAMINDEX write operation. See RAM Index operation for more information.

Note

Because the Data, Tag, and TLB arrays are greater than 32-bit wide, the processor contains multiple DL1DATA registers, to hold the array information.

Usage constraints

The accessibility to the DL1DATAn_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RWRWRWRWRW
Configurations

The DL1DATAn_EL1 is:

  • Common to the Secure and Non-secure states.

  • A 32-bit register in AArch64 state.

  • Architecturally mapped to the AArch32 DL1DATAn registers.

Attributes

See the register summary in Table 4.15.

Figure 4.55 shows the DL1DATAn_EL1 bit assignments.

Figure 4.55. DL1DATAn_EL1 bit assignments

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Table 4.72 shows the DL1DATAn_EL1 bit assignments.

Table 4.72. DL1DATAn_EL1 bit assignments

BitsNameFunction
[31:0]Data

Holds the data side L1 or L2 array information


To access the DL1DATAn_EL1 in AArch64 state, read or write the registers with:

MRS <Xt>, s3_0_c15_c1_n; Read EL1 Data L1 Data n Register
MSR s3_0_c15_c1_n, <Xt>; Write EL1 Data L1 Data n Register

n is 0, 1, 2, 3, or 4 for Opcode2 of the DL1DATAn_EL1 registers.

To access the DL1DATAn in AArch32 state, read or write the CP15 registers with:

MRC p15, 0, <Rt>, c15, c1, n; Read Data L1 Data n Register
MCR p15, 0, <Rt>, c15, c1, n; Write Data L1 Data n Register

n is 0, 1, 2, 3, or 4 for Opcode2 of the DL1DATAn registers.

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