4.3.14. AArch32 Instruction Set Attribute Register 2, EL1

The ID_ISAR2_EL1 characteristics are:

Purpose

Provides information about the instruction set that the processor supports in AArch32.

Usage constraints

The ID_ISAR2 must be interpreted with:

  • ID_ISAR0_EL1.

  • ID_ISAR1_EL1.

  • ID_ISAR3_EL1.

  • ID_ISAR4_EL1.

  • ID_ISAR5_EL1.

The accessibility to the ID_ISAR2_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

The ID_ISAR2_EL1 is:

  • Common to Secure and Non-secure states.

  • Architecturally mapped to the AArch32 ID_ISAR2 register.

Attributes

See the register summary in Table 4.1.

Figure 4.13 shows the ID_ISAR2_EL1 bit assignments.

Figure 4.13. ID_ISAR2_EL1 bit assignments

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Table 4.28 shows the ID_ISAR2_EL1 bit assignments.

Table 4.28. ID_ISAR2_EL1 bit assignments

BitsNameFunction
[31:28]Reversal

Returns 0x2 to indicate the processor implements the following Reversal instructions:

  • REV, REV16, and REVSH.

  • RBIT.

[27:24]PSR_AR

Returns 0x1 to indicate the processor implements the following instructions that can manipulate the PSR:

  • Processor supports MRS and MSR instructions, and the exception return forms of data-processing instructions. See the ARM® Architecture Reference Manual ARMv8 for more information.

[23:20]MultU

Returns 0x2 to indicate the processor implements the UMULL, UMLAL, and UMAAL unsigned multiply instructions.

[19:16]MultS

Returns 0x3 to indicate the processor implements the following signed multiply instructions:

  • SMULL and SMLAL instructions

  • SMLABB, SMLABT, SMLALBB,SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT instructions, and the Q bit in the PSRs.

  • SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions.

[15:12]Mult

Returns 0x2 to indicate the processor implements the MUL, MLA, and MLS multiply instructions.

[11:8]MultiAccessInt

Returns 0x0 to indicate no support for interruptible multi-access instructions. This means that the LDM and STM instructions are not interruptible.

[7:4]MemHint

Returns 0x4 to indicate the processor implements the PLD, PLI (NOP), and PLDW memory hint instructions.

[3:0]LoadStore

Returns 0x2 to indicate the processor implements the following additional load/store instructions and Load-Acquire/Store-Release instructions:

  • LDRD and STRD load/store instructions.

  • STRLB, STRLH, STRL, LDRAB, LDRAH, and LDRA Load-Acquire and Store-Release instructions.


To access the ID_ISAR2_EL1 in AArch64 state, read the register with:

MRS <Xt>, ID_ISAR2_EL1; Read AArch32 Instruction Set Attribute Register 2

To access the ID_ISAR2 in AArch32 state, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c2, 2; Read AArch32 Instruction Set Attribute Register 2
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