4.3.19. AArch64 Debug Feature Register 0, EL1

The ID_AA64DFR0_EL1 characteristics are:


Provides top-level information of the debug system in AArch64 state.

Usage constraints

The accessibility to the ID_AA64DFR0_EL1 by Exception level is:


The external debug accessibility to the ID_AA64DFR0[63:32] and the ID_AA64DFR0[31:0] by condition code is:


Table 10.1 describes the condition codes.


The ID_AA64DFR0_EL1 is architecturally mapped as follows:

  • [63:32] to external ID_AA64DFR0[63:32] register.

  • [31:0] to external ID_AA64DFR0[31:0] register.


See the register summary in Table 4.1.

Figure 4.18 shows the ID_AA64DFR0_EL1 bit assignments.

Figure 4.18. ID_AA64DFR0_EL1 bit assignments

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Table 4.33 shows the ID_AA64DFR0_EL1 bit assignments.

Table 4.33. ID_AA64DFR0_EL1 bit assignments


Reserved, res0

[31:28]CTX_CMPsReturns 0x1 to indicate support for two context-aware breakpoints

Reserved, res0

[23:20]WRPsReturns 0x3 to indicate support for four watchpoints

Reserved, res0

[15:12]BRPsReturns 0x5 to indicate support for six breakpoints

Returns 0x1 to indicate that the Performance Monitors (PMUv3) System registers are implemented

[7:4]TraceVerReturns 0x0 to indicate that the Trace System registers are not implemented
[3:0]DebugVerReturns 0x6 to indicate that the v8-A Debug architecture is implemented

To access the ID_AA64DFR0_EL1 in AArch64 state, read the register with:

MRS <Xt>, ID_AA64DFR0_EL1; Read AArch64 Debug Feature Register 0

The ID_AA64DFR0[31:0] can be accessed through the memory-mapped interface and the external debug interface, offset 0xD28.

The ID_AA64DFR0[63:32] can be accessed through the memory-mapped interface and the external debug interface, offset 0xD2C.

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