4.2.11. Security registers

Table 4.12 shows the Security registers in AArch64 state.

Table 4.12. AArch64 security registers

NameTypeResetWidthDescription
SCR_EL3RW0x0000000032

Secure Configuration Register, EL3 [a]

SDER32_EL3RW0x0000000032

Secure Debug Register, EL3 [a]

CPTR_EL3RW0x0000040032Architectural Feature Trap Register, EL3
MDCR_EL3RW0x0000000032

Monitor Debug Configuration Register, EL3 [a]

AFSR0_EL3RWres032Auxiliary Fault Status Register 0, EL1 and EL3
AFSR1_EL3RWres032Auxiliary Fault Status Register 1, EL1 and EL3
VBAR_EL3RWUNK[b]64

Vector Base Address Register, EL3 [a]

[a] See the ARM® Architecture Reference Manual ARMv8 for more information.

[b] The reset value of bits[63:32] is 0x00000000.


Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914