4.3.66. CPU Auxiliary Control Register, EL1

The CPUACTLR_EL1 characteristics are:

Purpose

Provides implementation defined configuration and control options for the processor. There is one 64-bit CPU Auxiliary Control Register for each processor in the Cortex-A57 MPCore device.

Usage constraints

The accessibility to the CPUACTLR_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RW[a]RW[a]RW[b]RWRW

[a] Write access if ACTLR_EL3.CPUACTLR is 1 and ACTLR_EL2.CPUACTLR is 1, or ACTLR_EL3.CPUACTLR is 1 and SCR.NS is 0.

[b] Write access if ACTLR_EL3.CPUACTLR is 1.

The CPU Auxiliary Control Register can only be written when the system is idle. ARM recommends that you write to this register after a powerup reset, before the MMU is enabled, and before any ACE or ACP traffic begins.

Note

Setting many of these bits can cause significantly lower performance on your code. Therefore, it is suggested that you do not modify this register unless directed by ARM.

Configurations

CPUACTLR_EL1 is:

  • Common to the Secure and Non-secure states.

  • A 64-bit read/write register.

  • Architecturally mapped to the AArch32 CPUACTLR register.

Attributes

See the register summary in Table 4.15.

Figure 4.73 shows the CPUACTLR_EL1[63:32] bit assignments.

Figure 4.73. CPUACTLR_EL1[63:32] bit assignments

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Table 4.75 shows the CPUACTLR_EL1[63:32] bit assignments.

Table 4.75. CPUACTLR_EL1[63:32] bit assignments

BitsNameFunction
[63][a]Force processor RCG enables active

Forces processor RCG enables active:

0

Enables the processor RCGs for additional clock gating and potentially reduce dynamic power dissipation. This is the reset value.

1

Forces the processor RCG enables HIGH.

Setting this bit to 1 has no effect if the multiprocessor is configured to not include RCGs. See Regional clock gating.

[62:60]-

Reserved, res0.

[59][a]Disable load pass DMB

Disables load pass DMB. This does not include the implicit barrier from Load-Acquire and Load-Acquire Exclusive. The possible values are:

0

Enables load pass DMB. This is the reset value.

1

Disables load pass DMB.

[58][a]Disable DMB nullification

Disables DMB nullification. This includes the implicit barrier from Store-Release and Store-Release Exclusive:

0

Enables DMB nullification. This is the reset value.

1

Disables DMB nullification.

[57][a]

Treat DMB st/st and DMB ld/all as DMB all/all.

Treat DSB st/st and DSB ld/all as DSB all/all.

Treats DMB st/st and DMB ld/all as DMB all/all. Treat DSB st/st and DSB ld/all as DSB all/all. This does not include the implicit barrier from Load-Acquire/Store-Release. The possible values are:

0

Normal behavior. This the reset value.

1
  • Treat DMB st/st and DMB ld/all as DMB all/all.

  • Treat DSB st/st and DSB ld/all as DSB all/all.

[56][a]Disable L1 Data Cache hardware prefetcher

Disables L1 Data Cache hardware prefetcher:

0

Enables L1 Data Cache hardware prefetcher. This the reset value.

1

Disables L1 Data Cache hardware prefetcher.

[55][a]Disable load pass store

Disables load pass store:

0

Enables load pass store. This the reset value.

1

Disables load pass store.

[54][a]Treat GRE/nGRE as nGnRE

Treat GRE and nGRE as nGnRE:

0

Enables optimization for GRE and nGRE load/store. This is the reset value.

1

Treats GRE and nGRE as nGnRE. Disables optimization for GRE and nGRE load/store.

[53][a]

Treat DMB and DSB as if their domain field is SY

Treats DMB and DSB as if their domain field is SY. The possible values are:

0

Normal behavior. This is the reset value.

1

Treat DMB NSH, DMB ISH, and DMB OSH as DMB SY.

Treat DSB NSH, DSB ISH, and DSB OSH as DSB SY.

[52][a]

Disable over-read from LDNP instruction

Disables over-read from LDNP instruction:

0

Enables the over-read from LDNP instruction. This is the reset value.

1

Disables the over-read from LDNP instruction.

[51][a]

Disable contention detection and fast exclusive monitor path

Disables contention detection and fast exclusive monitor path:

0

Enables contention detection and fast exclusive monitor path. This is the reset value.

1

Disables contention detection and fast exclusive monitor path.

[50][a]Disable store streaming on NC/GRE memory type

Disables store streaming on NC/GRE memory type:

0

Enables store streaming on NC/GRE memory type. This is the reset value.

1

Disables store streaming on NC/GRE memory type.

[49][a]Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type

Disables non-allocate hint of Write-Back No-Allocate memory type:

0

Enables non-allocate hint of WBNA memory type. This is the reset value.

1

Disables non-allocate hint of WBNA memory type.

[48][a]Disable early speculative read access from LS to L2

Disables early speculative read access from LS to L2:

0

Enables speculative early read access from LS to L2. This is the reset value.

1

Disables speculative early read access from LS to L2.

[47][a]Disable L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger.

Disables L1 and L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger:

0

Enables L1/L2 hardware prefetch across 4KB page boundary if the page is 64KB or larger. This is the reset value.

1

Disables L1/L2 hardware prefetch across 4KB page boundary even if the page is 64KB or larger.

[46:45]-Reserved, res0.
[44][a]Enable data cache clean as data cache clean/invalidate

Enables data cache clean as data cache clean and invalidate:

0

Normal behavior, executes data cache clean as data cache clean.

This is the reset value.

1

Executes data cache clean as data cache clean and invalidate.

[43:40]-

Reserved, res0.

[39][a][b]Disable instruction merging

Disables instruction merging:

0

Enables instruction merging. This is the reset value.

1

Disables instruction merging.

[38][a]Force FPSCR write flush

Forces FPSCR write flush:

0

Normal behavior for FPSCR writes. This is the reset value.

1

Forces synchronizing flush on all FPSCR writes.

[37][a]Disable instruction group split

Disables instruction group split:

0

Enables instruction group split. This is the reset value.

1

Disables instruction group split.

[36][a]Force implicit DSB on an ISB event

Forces implicit DSB on ISB event:

0

Normal behavior. This is the reset value.

1

Force implicit DSB on an ISB event.

[35]-

Reserved, res0.

[34][a]Disable Static Branch Predictor

Disables static branch predictor:

0

Enables static branch predictor. This is the reset value.

1

Disables static branch predictor.

[33][a]Disable L1 Instruction Cache way prediction in micro-BTB

Disables L1 Instruction Cache way prediction in micro-BTB:

0

Enables Instruction Cache way prediction in micro-BTB. This is the reset value.

1

Disables Instruction Cache way prediction in micro-BTB.

[32][a]Disable L1 Instruction Cache prefetch

Disables L1 Instruction Cache prefetch:

0

Enables Instruction Cache prefetch. This is the reset value.

1

Disables Instruction Cache prefetch.

[a] This bit is used internally for debugging and characterization purposes only. For normal operation, ARM recommends that you do not change the value of this bit from its reset value.

[b] This is bit is not available in revisions prior to r0p1.


Figure 4.74 shows the CPUACTLR_EL1[31:0] bit assignments.

Figure 4.74. CPUACTLR_EL1[31:0] bit assignments

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Table 4.76 shows the CPUACTLR_EL1[31:0] bit assignments.

Table 4.76. CPUACTLR_EL1[31:0] bit assignments

BitsNameFunction
[31][a]Snoop-delayed exclusive handling

Snoop-delayed exclusive handling. The possible values are:

0

Normal exclusive handling behavior. This is the reset value.

1

Modifies exclusive handling behavior by delaying certain snoop requests.

[30][a]Force main clock enable active

Forces main clock enable active. The possible values are:

0

Does not prevent the clock generator from stopping the processor clock. This is the reset value.

1

Prevents the clock generator from stopping the processor clock.

If the processor dynamic retention feature is used then this bit must be zero. See Processor dynamic retention.

[29][a]Force Advanced SIMD and floating-point clock enable active

Forces Advanced SIMD and Floating-point clock enable active. The possible values are:

0

Does not prevent the clock generator from stopping the Advanced SIMD and Floating-point clock. This is the reset value.

1

Prevents the clock generator from stopping the Advanced SIMD and Floating-point clock.

See Advanced SIMD and FP clock gating.

If the processor dynamic retention feature is used then this bit must be zero. See Processor dynamic retention.

[28:27]Write streaming no-allocate threshold

Write streaming no-allocate threshold. The possible values are:

0b00

12th consecutive streaming cache line does not allocate in the L1 or L2 cache. This is the reset value.

0b01

128th consecutive streaming cache line does not allocate in the L1 or L2 cache.

0b10

512th consecutive streaming cache line does not allocate in the L1 or L2 cache.

0b11

Disables streaming. All Write-Allocate lines allocate in the L1 or L2 cache.

[26:25]Write streaming no-L1-allocate threshold

Write streaming no-L1-allocate threshold. The possible values are:

0b00

4th consecutive streaming cache line does not allocate in the L1 cache. This is the reset value.

0b01

64th consecutive streaming cache line does not allocate in the L1 cache.

0b10

128th consecutive streaming cache line does not allocate in the L1 cache.

0b11

Disables streaming. All Write-Allocate lines allocate in the L1 cache.

[24]Non-cacheable streaming enhancement

Non-cacheable streaming enhancement. You can set this bit only if your memory system meets the requirement that cache line fill requests from the Cortex-A57 MPCore processor are atomic. The possible values are:

0

Disables higher performance Non-cacheable load forwarding. This is the reset value.

1

Enables higher performance Non-cacheable load forwarding. See Non-cacheable streaming enhancement for more information.

[23][a]Force in-order requests to the same set and way

Forces in-order requests to the same set and way. The possible values are:

0

Does not force in-order requests to the same set and way. This is the reset value.

1

Forces in-order requests to the same set and way.

[22][a]Force in-order load issue

Forces in-order load issue. The possible values are:

0

Does not force in-order load issue. This is the reset value.

1

Forces in-order load issue.

[21][a]Disable L2 TLB prefetching

Disables L2 TLB prefetching. The possible values are:

0

Enables L2 TLB prefetching. This is the reset value.

1

Disables L2 TLB prefetching.

[20][a]Disable L2 translation table walk IPA PA cache

Disables L2 translation table walk Immediate Physical Address (IPA) to Physical Address (PA) cache. The possible values are:

0

Enables L2 translation table walk IPA to PA cache. This is the reset value.

1

Disables L2 translation table walk IPA to PA cache.

[19][a]Disable L2 stage 1 translation table walk cache

Disables L2 stage 1 translation table walk cache. The possible values are:

0

Enables L2 stage 1 translation table walk cache. This is the reset value.

1

Disables L2 stage 1 translation table walk cache.

[18][a]Disable L2 stage 1 translation table walk L2 PA cache

Disables L2 stage 1 translation table walk L2 PA cache. The possible values are:

0

Enables L2 stage 1 translation table walk L2 PA cache. This is the reset value.

1

Disables L2 stage 1 translation table walk L2 PA cache.

[17][a]Disable L2 TLB performance optimization

Disables L2 TLB performance optimization. The possible values are

0

Enables L2 TLB optimization. This is the reset value.

1

Disables L2 TLB optimization.

[16][a]Enable full Strongly-ordered and Device load replay

Enables full Strongly-ordered or Device load replay. The possible values are:

0

Disables full Strongly-ordered or Device load replay. This is the reset value.

1

Enables full Strongly-ordered or Device load replay.

[15][a]Force in-order issue in branch execute unit

Forces in-order issue in branch execute unit. The possible values are:

0

Disables forced in-order issue. This is the reset value.

1

Forces in-order issue.

[14][a]Force limit of one instruction group commit/de-allocate per cycle

Forces limit of one instruction group to commit and de-allocate per cycle. The possible values are:

0

Normal commit and de-allocate behavior. This is the reset value.

1

Limits commit and de-allocate to one instruction group per cycle.

[13][a]Flush after Special Purpose Register (SPR) writes

Flushes after certain SPR writes. The possible values are:

0

Normal behavior for SPR writes. This is the reset value.

1

Flushes after certain SPR writes.

[12][a]Force push of SPRs

Forces push of certain SPRs from local dispatch copies to shadow copies. The possible values are:

0

Normal behavior for SPRs. This is the reset value.

1

Pushes certain SPRs from local dispatch copies to shadow copies.

Note

Setting this bit to 1 forces the processor to behave as if bit[13] is set to 1.

[11][a]Limit to one instruction per instruction group

Limits to one instruction per instruction group. The possible values are:

0

Normal instruction grouping. This is the reset value.

1

Limits to one instruction per instruction group.

[10][a]Force serialization after each instruction group

Forces serialization after each instruction group. The possible values are:

0

Disables forced serialization after each instruction group. This is the reset value.

1

Forces serialization after each instruction group.

Note

Setting this bit to 1 forces the processor to behave as if bit[11] is set to 1.

[9][a]Disable flag renaming optimization

Disables flag renaming optimization. The possible values are:

0

Enables normal flag renaming optimization. This is the reset value.

1

Disables normal flag renaming optimization.

[8][a]Execute WFI instruction as a NOP instruction

Executes WFI instruction as a NOP instruction. The possible values are:

0

Executes WFI instruction as defined in the ARM® Architecture Reference Manual ARMv8. This is the reset value.

1

Executes WFI instruction as a NOP instruction, and does not put the processor in WFI low-power state.

[7][a]Execute WFE instruction as a NOP instruction

Executes WFE instruction as a NOP instruction. The possible values are:

0

Executes WFE instruction as defined in the ARM® Architecture Reference Manual ARMv8. This is the reset value.

1

Executes WFE instruction as a NOP instruction, and does not put the processor in WFE low-power state.

[6]-Reserved, res0.
[5][a]Execute PLD and PLDW instructions as a NOP

Executes PLD and PLDW instructions as a NOP instruction. The possible values are:

0

Executes PLD and PLDW instructions as defined in the ARM® Architecture Reference Manual ARMv8. This is the reset value.

1

Executes PLD and PLDW instructions as a NOP instruction.

[4][a]Disable indirect predictor

Disables indirect predictor. The possible values are:

0

Enables indirect predictor. This is the reset value.

1

Disables indirect predictor.

[3][a]Disable micro-BTB

Disables micro-Branch Target Buffer (BTB). The possible values are:

0

Enables micro-BTB. This is the reset value.

1

Disables micro-BTB.

[2]-Reserved, res0.
[1][a]Disable Instruction Cache miss streaming

Disables Instruction Cache miss streaming. The possible values are:

0

Enables Instruction Cache miss streaming. Sequential fetches resulting from Instruction Cache misses wait until individual packets arrive. This is the reset value.

1

Disables Instruction Cache miss streaming. Sequential fetches resulting from Instruction Cache misses internally generate misses for each packet.

[0][a]

Enable invalidates of BTB

Enables invalidate of BTB. The possible values are:

0

The Invalidate Instruction Cache All and Invalidate Instruction Cache by VA instructions only invalidates the instruction cache array. This is the reset value.

1

The Invalidate Instruction Cache All and Invalidate Instruction Cache by VA instructions invalidates the instruction cache array and branch target buffer.

[a] This bit is used internally for debugging and characterization purposes only. For normal operation, ARM recommends that you do not change the value of this bit from its reset value.


To access the CPUACTLR_EL1 in AArch64 state, read or write the register with:

MRS <Xt>, S3_1_c15_c2_0; Read EL1 CPU Auxiliary Control Register
MSR S3_1_c15_c2_0, <Xt>; Write EL1 CPU Auxiliary Control Register

To access the CPUACTLR in AArch32 state, read or write the CP15 register with:

MRRC p15, 0, <Rt>, <Rt2>, c15; Read CPU Auxiliary Control Register
MCRR p15, 0, <Rt>, <Rt2>, c15; Write CPU Auxiliary Control Register
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