4.2.1. AArch64 identification registers

Table 4.1 shows the identification registers in AArch64 state. Bits[63:32] are reset to 0x00000000 for all 64-bit registers in Table 4.1.

Table 4.1. AArch64 identification registers

NameTypeResetWidthDescription
MIDR_EL1RO0x411FD07132

Main ID Register, EL1

MPIDR_EL1RO0x80000003[a]64

Multiprocessor Affinity Register, EL1

REVIDR_EL1RO0x0000000032

Revision ID Register, EL1

ID_PFR0_EL1RO0x0000013132

AArch32 Processor Feature Register 0, EL1

ID_PFR1_EL1RO0x00011011[b]32

AArch32 Processor Feature Register 1, EL1

ID_DFR0_EL1RO0x0301006632

AArch32 Debug Feature Register 0, EL1

ID_AFR0_EL1RO0x0000000032AArch32 Auxiliary Feature Register 0, EL1
ID_MMFR0_EL1RO0x1010110532

AArch32 Memory Model Feature Register 0, EL1

ID_MMFR1_EL1RO0x4000000032

AArch32 Memory Model Feature Register 1, EL1

ID_MMFR2_EL1RO0x0126000032

AArch32 Memory Model Feature Register 2, EL1

ID_MMFR3_EL1RO0x0210221132

AArch32 Memory Model Feature Register 3, EL1

ID_ISAR0_EL1RO0x0210111032

AArch32 Instruction Set Attribute Register 0, EL1

ID_ISAR1_EL1RO0x1311211132

AArch32 Instruction Set Attribute Register 1, EL1

ID_ISAR2_EL1RO0x2123204232

AArch32 Instruction Set Attribute Register 2, EL1

ID_ISAR3_EL1RO0x0111213132

AArch32 Instruction Set Attribute Register 3, EL1

ID_ISAR4_EL1RO0x0001114232

AArch32 Instruction Set Attribute Register 4, EL1

ID_ISAR5_EL1RO0x00010001[c]32

AArch32 Instruction Set Attribute Register 5, EL1

ID_AA64PFR0_EL1RO0x0000222264AArch64 Processor Feature Register 0, EL1
ID_AA64DFR0_EL1RO0x1030510664AArch64 Debug Feature Register 0, EL1
ID_AA64ISAR0_EL1RO0x00010000[d]64AArch64 Instruction Set Attribute Register 0, EL1
ID_AA64MMFR0_EL1RO0x0000112464AArch64 Memory Model Feature Register 0, EL1
CCSIDR_EL1ROUNK32

Cache Size ID Register, EL1

CLIDR_EL1RO0x0A20002332

Cache Level ID Register, EL1

AIDR_EL1-0x0000000032

Auxiliary ID Register, EL1

CSSELR_EL1RWUNK32Cache Size Selection Register, EL1
CTR_EL0RO0x8444C00432Cache Type Register, EL0
DCZID_EL0RO0x0000000432Data Cache Zero ID, EL0
VPIDR_EL2RW-[e]32Virtualization Processor ID Register, EL2
VMPIDR_EL2RO-[f]64Multiprocessor Affinity Register, EL1

[a] The reset value depends on the primary inputs, CLUSTERIDAFF1 and CLUSTERIDAFF2, and the number of processors that the MPCore device implements. The value shown is for a four processor implementation, with CLUSTERIDAFF1 and CLUSTERIDAFF2 set to zero.

[b] The reset value depends on the primary input GICCDISABLE. The value shown assumes the GICCDISABLE signal is tied HIGH.

[c] The reset value is 0x00011121 if the Cryptography engine is implemented.

[d] The reset value is 0x00011120 if the Cryptography engine is implemented.

[e] The reset value is the value of the Main ID Register.

[f] The reset value is the value of the Multiprocessor Affinity Register.


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