14.6.1. Floating-point System ID Register

The FPSID characteristics are:

Purpose

Provides top-level information about the floating-point implementation.

Usage constraints

The accessibility to the FPSID by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-ConfigROConfigConfigRO
Configurations

The FPSID is Common to Secure and Non-secure states.

Attributes

See the register summary in Table 14.9.

Figure 14.7 shows the FPSID bit assignments.

Figure 14.7. FPSID bit assignments

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Table 14.10 shows the FPSID bit assignments.

Table 14.10. FPSID bit assignments

BitsNameFunction
[31:24]Implementer

Indicates the implementer:

0x41

ARM Limited.

[23]SW

Software bit. This bit indicates whether a system provides only software emulation of the floating-point instructions:

0x0

The system includes hardware support for floating-point operations.

[22:16]Subarchitecture

Subarchitecture version number:

0x03

VFPv3 architecture, or later, with no subarchitecture. The entire floating-point implementation is in hardware, and no software support code is required.

The VFP architecture version is indicated by the MVFR0, MVFR1, and MVFR2 registers.

[15:8]PartNum

Indicates the part number for the floating-point implementation:

0x40

VFP.

[7:4]Variant

Indicates the variant number:

0x7

Cortex-A57 MPCore processor.

[3:0]Revision

Indicates the revision number for the floating-point implementation:

0x0

Revision.


To access the FPSID register, see Programmers model for Advanced SIMD and Floating-point.

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