4.3.41. Translation Control Register, EL1

The TCR_EL1 characteristics are:

Purpose

Controls which Translation Base Register defines the base address register for a translation table walk required for stage 1 translation of a memory access from EL0 or EL1. Also controls the translation table format and holds cacheability and shareability information.

Usage constraints

The accessibility of the TCR_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RWRWRWRWRW
Configurations

TCR_EL1[31:0] is architecturally mapped to the Non-secure AArch32 TTBCR register. See Translation Table Base Control Register for more information.

Attributes

See the register summary in Table 4.3.

Figure 4.37 shows the TCR_EL1 bit assignments.

Figure 4.37. TCR_EL1 bit assignments

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Table 4.53 shows the TCR_EL1 bit assignments.

Table 4.53.  TCR_EL1 bit assignments

BitsNameFunction
[63:39]-

Reserved, res0.

[38]TBI1

Top Byte Ignored. Indicates whether the top byte of the input address is used for address match for the TTBR1 region. The values are:

0

Top byte used in the address calculation.

1

Top byte ignored in the address calculation.

[37]TBI0

Top Byte Ignored. Indicates whether the top byte of the input address is used for address match for the TTBR0 region. The values are:

0

Top byte used in the address calculation.

1

Top byte ignored in the address calculation.

[36]AS

ASID size. The values are:

0

8-bit.

1

16-bit.

[35]-

Reserved, res0.

[34:32]IPS

Intermediate Physical Address Size. The possible values are:

0b000

32-bit, 4GBytes.

0b001

36-bit, 64GBytes.

0b010

40-bit, 1TByte.

0b011

42-bit, 4TBytes.

0b100

44-bit, 16TBytes.

0b101

48-bit, 256TBytes.

[31]-

Reserved, res1.

[30]TG1

TTBR1_EL1 granule size. The values are:

0

4KB.

1

64KB.

[29:28]SH1

Shareability attribute for memory associated with translation table walks using TTBR1. The values are:

0b00

Non-shareable.

0b01

Reserved.

0b10

Outer Shareable.

0b11

Inner Shareable.

[27:26]ORGN1

Outer cacheability attribute for memory associated with translation table walks using TTBR1. The values are:

0b00

Normal memory, Outer Non-cacheable.

0b01

Normal memory, Outer Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Outer Write-Through Cacheable.

0b11

Normal memory, Outer Write-Back no Write-Allocate Cacheable.

[25:24]IRGN1

Inner cacheability attribute for memory associated with translation table walks using TTBR1. The values are:

0b00

Normal memory, Inner Non-cacheable.

0b01

Normal memory, Inner Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Inner Write-Through Cacheable.

0b11

Normal memory, Inner Write-Back no Write-Allocate Cacheable.

[23]EPD1

Translation table walk disable for translations using TTBR1. Controls if a translation table walk is performed on a TLB miss for an address that is translated using TTBR1. The values are:

0

Perform translation table walk using TTBR1.

1

A TLB miss on an address translated from TTBR1 generates a Translation fault. No translation table walk is performed.

[22]A1

Selects whether TTBR0 or TTBR1 defines the ASID. The values are:

0

TTBR0.ASID defines the ASID.

1

TTBR1.ASID defines the ASID.

[21:16]T1SZ

Size offset of the memory region addressed by TTBR1. The region size is 2(32-TSIZE) bytes.

[15]-

Reserved, res0.

[14]TG0

TTBR0_EL1 granule size. The values are:

0

4KB.

1

64KB.

[13:12]SH0

Shareability attribute for memory associated with translation table walks using TTBR0. The values are:

0b00

Non-shareable.

0b01

Reserved.

0b10

Outer Shareable.

0b11

Inner Shareable.

[11:10]ORGN0

Outer cacheability attribute for memory associated with translation table walks using TTBR0. The values are:

0b00

Normal memory, Outer Non-cacheable.

0b01

Normal memory, Outer Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Outer Write-Through Cacheable.

0b11

Normal memory, Outer Write-Back no Write-Allocate Cacheable.

[9:8]IRGN0

Inner cacheability attribute for memory associated with translation table walks using TTBR0. The values are:

0b00

Normal memory, Inner Non-cacheable.

0b01

Normal memory, Inner Write-Back Write-Allocate Cacheable.

0b10

Normal memory, Inner Write-Through Cacheable.

0b11

Normal memory, Inner Write-Back no Write-Allocate Cacheable.

[7:6]-

Reserved, res0.

[5:0]T0SZ

Size offset of the memory region addressed by TTBR0. The region size is 2(32-TSIZE) bytes.


To access the TCR_EL1 in AArch64 state, read or write the register with:

MRS <Xt>, TCR_EL1; Read EL1 Translation Control Register
MSR TCR_EL1, <Xt>; Write EL1 Translation Control Register
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