4.4.26. Performance Monitors registers

Table 4.108 shows the Performance Monitors registers in AArch32 state.

Table 4.108. Performance Monitors registers

NameCRnop1CRmop2TypeResetDescription
PMCRc90c120RW0x41013000Performance Monitors Control Register. See Performance Monitors Control Register, EL0.
PMCNTENSET  1RWUNKPerformance Monitors Count Enable Set Register. [a]
PMCNTENCLR  2RWUNKPerformance Monitors Count Enable Clear Register. [a]
PMOVSR  3RWUNKPerformance Monitors Overflow Flag Status Register. [a]
PMSWINC  4WO-Performance Monitors Software Increment Register. [a]
PMSELR  5RWUNKPerformance Monitors Event Counter Selection Register. [a]
PMCEID0  6RO0x7FFF0F3FPerformance Monitors Common Event Identification Register 0. See Performance Monitors Common Event Identification Register 0, EL0.
PMCEID1  7ROUNKPerformance Monitors Common Event Identification Register 1. [a]
PMCCNTR  c130RWUNKPerformance Monitors Cycle Count Register. [a]
PMXEVTYPER  1RWUNKPerformance Monitors Selected Event Type Register. [a]
PMCCFILTR   RW0x00000000Performance Monitors Cycle Count Filter Register. [a]
PMXEVCNTR  2RWUNKPerformance Monitors Selected Event Count Register. [a]
PMUSERENR  c140RW0x00000000Performance Monitors User Enable Register. [a]
PMINTENSET  1RWUNKPerformance Monitors Interrupt Enable Set Register. [a]
PMINTENCLR  2RWUNKPerformance Monitors Interrupt Enable Clear Register. [a]
PMOVSSET  3RWUNKPerformance Monitors Overflow Flag Status Set Register. [a]

[a] See the ARM® Architecture Reference Manual ARMv8 for more information.


Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914