4.3.5. AArch32 Processor Feature Register 1, EL1

The ID_PFR1_EL1 characteristics are:

Purpose

Provides information about the programmers model and extensions support in AArch32.

Usage constraints

The ID_PFR1_EL1 must be interpreted with the ID_PFR0_EL1.

The accessibility to the ID_PFR1_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

The ID_PFR1_EL1 is:

  • Common to Secure and Non-secure states.

  • Architecturally mapped to the AArch32 ID_PFR1 register.

Attributes

See the register summary in Table 4.1.

Figure 4.5 shows the ID_PFR1_EL1 bit assignments.

Figure 4.5. ID_PFR1_EL1 bit assignments

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Table 4.20 shows the ID_PFR1_EL1 bit assignments.

Table 4.20. ID_PFR1_EL1 bit assignments

BitsNameFunction
[31:28]GIC CP15

Indicates support for the GIC CP15 interface. The possible values are:

0x0

No GIC CP15 registers are supported. This is the reset value when GICCDISABLE is tied HIGH.

0x1

GICv3 CP15 registers are supported. This is the reset value when GICCDISABLE is tied LOW.

[27:20]-

Reserved, res0.

[19:16]GenTimer

Indicates support for Generic Timer Extension. This value is:

0x1

Processor supports Generic Timer Extension.

[15:12]Virtualization

Indicates support for Virtualization Extensions. This value is:

0x1

Processor supports Virtualization Extensions.

[11:8]MProgMod

Indicates support for M-profile programmers model. This value is:

0x0

Processor does not support M-profile programmers model.

[7:4]Security

Indicates support for Security Extensions. This value is:

0x1

Processor supports Security Extensions. This includes support for Monitor mode and the SMC instruction.

[3:0]ProgrMod

Indicates support for the standard programmers model for ARMv4 and later. This value is:

0x1

Processor supports the standard programmers model for ARMv4 and later. The model supports User, FIQ, IRQ, Supervisor, Abort, Undefined, and System modes.


To access the ID_PFR1_EL1 in AArch64 state, read the register with:

MRS <Xt>, ID_PFR1_EL1; Read AArch32 Processor Feature Register 1

To access the ID_PFR1 in AArch32 state, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c1, 1; Read AArch32 Processor Feature Register 1
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