4.2.7. AArch64 address translation operations

Table 4.7 shows the address translation register in AArch64 state.

Table 4.7. AArch64 address translation register

NameTypeResetWidthDescription
PAR_EL1RWUNK [a]64Physical Address Register, EL1

[a] Bits[63:32] are reset to 0x00000000.


Table 4.8 shows the System instructions for address translation operations in AArch64 state. See the ARM® Architecture Reference Manual ARMv8 for more information.

Table 4.8. AArch64 address translation operations

NameDescription
AT S1E1R

Stage 1 current state EL1 read

AT S1E1W

Stage 1 current state EL1 write

AT S1E0RStage 1 current state unprivileged read
AT S1E0WStage 1 current state unprivileged write
AT S1E2R

Stage 1 Hyp mode read

AT S1E2WStage 1 Hyp mode write
AT S12E1RStages 1 and 2 Non-secure EL1 read
AT S12E1W

Stages 1 and 2 Non-secure EL1 write

AT S12E0R

Stages 1 and 2 Non-secure unprivileged read

AT S12E0W

Stages 1 and 2 Non-secure unprivileged write

AT S1E3R

Stage 1 current state EL3 read

AT S1E3W

Stage 1 current state EL3 write


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