4.3.9. AArch32 Memory Model Feature Register 1, EL1

The ID_MMFR1_EL1 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support in AArch32.

Usage constraints

The ID_MMFR1_EL1 must be interpreted with:

  • ID_MMFR0_EL1.

  • ID_MMFR2_EL1.

  • ID_MMFR3_EL1.

The accessibility to the ID_MMFR1_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

The ID_MMFR1_EL1 is:

  • Common to Secure and Non-secure states.

  • Architecturally mapped to the AArch32 ID_MMFR1 register.

Attributes

See the register summary in Table 4.1.

Figure 4.8 shows the ID_MMFR1_EL1 bit assignments.

Figure 4.8. ID_MMFR1_EL1 bit assignments

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Table 4.23 shows the ID_MMFR1 bit assignments.

Table 4.23. ID_MMFR1_EL1 bit assignments

BitsNameFunction
[31:28]BPred

Indicates branch predictor management requirements. This value is:

0x4

Branch predictor does not require flushing at any time.

[27:24]L1TstCln

Indicates the supported L1 data cache test and clean operations, for Harvard or unified cache implementation. This value is:

0x0

Not supported.

[23:20]L1Uni

Indicates the supported entire L1 cache maintenance operations, for a unified cache implementation. This value is:

0x0

Not supported.

[19:16]L1Hvd

Indicates the supported entire L1 cache maintenance operations, for a Harvard cache implementation. This value is:

0x0

Not supported.

[15:12]L1UniSW

Indicates the supported L1 cache line maintenance operations by set/way, for a unified cache implementation. This value is:

0x0

Not supported.

[11:8]L1HvdSW

Indicates the supported L1 cache line maintenance operations by set/way, for a Harvard cache implementation. This value is:

0x0

Not supported.

[7:4]L1UniVA

Indicates the supported L1 cache line maintenance operations by VA, for a unified cache implementation. This value is:

0x0

Not supported.

[3:0]L1HvdVA

Indicates the supported L1 cache line maintenance operations by VA, for a Harvard cache implementation. This value is:

0x0

Not supported.


To access the ID_MMFR1_EL1 in AArch64 state, read the register with:

MRS <Xt>, ID_MMFR1_EL1; Read AArch32 Memory Model Feature Register 1

To access the ID_MMFR1 in AArch32 state, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c1, 5; Read AArch32 Memory Model Feature Register 1
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