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Home > System Control > AArch64 register descriptions > Cache Size ID Register, EL1 |
The CCSIDR_EL1 characteristics are:
Provides information about the architecture of the caches. There is one Cache Size ID Register for each cache that the processor can access. CSSELR_EL1 selects which Cache Size ID Register is accessible.
The accessibility to the CCSIDR_EL1 by Exception level is:
EL0 | EL1(NS) | EL1(S) | EL2 | EL3(SCR.NS = 1) | EL3(SCR.NS = 0) |
---|---|---|---|---|---|
- | RO | RO | RO | RO | RO |
If CSSELR_EL1 indicates a cache that is not implemented, reading the Cache Size ID Register returns an unknown value.
The CCSIDR_EL1 is:
Common to Secure and Non-secure states.
Architecturally mapped to the AArch32 CCSIDR register.
See the register summary in Table 4.1.
Figure 4.21 shows the CCSIDR_EL1 bit assignments.
Table 4.36 shows the CCSIDR_EL1 bit assignments.
Table 4.36. CCSIDR_EL1 bit assignments
Bits | Name | Function |
---|---|---|
[31] | WT | Returns 0b0 to indicate
that the cache level does not support Write-Through. |
[30] | WB | Indicates support for Write-Back. The possible values are:
|
[29] | RA | Returns 0b1 to indicate
that the cache level supports Read-Allocation. |
[28] | WA | Indicates support for Write-Allocation. The possible values are:
|
[27:13] | NumSets | Indicates the (number of sets in cache) - 1. Therefore, a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2. |
[12:3] | Associativity | Indicates the associativity of the selected cache level. The possible values are:
|
[2:0] | LineSize | Returns |
Table 4.37 shows the individual bit field and complete register encoding for the CCSIDR_EL1. The CSSELR_EL1 determines which Cache Size ID Register to select.
Table 4.37. Encoding of the Cache Size ID Register
CSSELR_EL1 | Size | Complete register encoding | Register bit field encoding | ||||||
---|---|---|---|---|---|---|---|---|---|
WT | WB | RA | WA | NumSets | Associativity | LineSize | |||
0x0 | 32KB | 0x701FE00A | 0 | 1 | 1 | 1 | 0x0FF | 0x1 | 0x2 |
0x1 | 48KB | 0x201FE012 | 0 | 0 | 1 | 0 | 0x0FF | 0x2 | 0x2 |
0x2 | 512KB | 0x703FE07A | 0 | 1 | 1 | 1 | 0x1FF | 0xF | 0x2 |
1024KB | 0x707FE07A | 0 | 1 | 1 | 1 | 0x3FF | 0xF | 0x2 | |
2048KB | 0x70FFE07A | 0 | 1 | 1 | 1 | 0x7FF | 0xF | 0x2 | |
0x3 -0xF | - | - | Reserved |
To access the CCSIDR_EL1 in AArch64 state, read the register with:
MRS <Xt>, CCSIDR_EL1; Read Cache Size ID Register
To access the CCSIDR in AArch32 state, read the CP15 register with:
MRC p15, 1, <Rt>, c0, c0, 0; Read Cache Size ID Register