4.3.22. Cache Size ID Register, EL1

The CCSIDR_EL1 characteristics are:

Purpose

Provides information about the architecture of the caches. There is one Cache Size ID Register for each cache that the processor can access. CSSELR_EL1 selects which Cache Size ID Register is accessible.

Usage constraints

The accessibility to the CCSIDR_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO

If CSSELR_EL1 indicates a cache that is not implemented, reading the Cache Size ID Register returns an unknown value.

Configurations

The CCSIDR_EL1 is:

  • Common to Secure and Non-secure states.

  • Architecturally mapped to the AArch32 CCSIDR register.

Attributes

See the register summary in Table 4.1.

Figure 4.21 shows the CCSIDR_EL1 bit assignments.

Figure 4.21. CCSIDR_EL1 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.36 shows the CCSIDR_EL1 bit assignments.

Table 4.36. CCSIDR_EL1 bit assignments

BitsNameFunction
[31]WTReturns 0b0 to indicate that the cache level does not support Write-Through.
[30]WB

Indicates support for Write-Back. The possible values are:

0

Cache level does not support Write-Back.

1

Cache level supports Write-Back.

[29]RAReturns 0b1 to indicate that the cache level supports Read-Allocation.
[28]WA

Indicates support for Write-Allocation. The possible values are:

0

Cache level does not support Write-Allocation.

1

Cache level supports Write-Allocation.

[27:13]NumSets

Indicates the (number of sets in cache) - 1. Therefore, a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2.

[12:3]Associativity

Indicates the associativity of the selected cache level. The possible values are:

0b0000000001

2-way.

0b0000000010

3-way.

0b0000001111

16-way.

[2:0]LineSize

Returns 0b010 to indicate that the cache line size is 64 bytes.


Table 4.37 shows the individual bit field and complete register encoding for the CCSIDR_EL1. The CSSELR_EL1 determines which Cache Size ID Register to select.

Table 4.37. Encoding of the Cache Size ID Register

CSSELR_EL1SizeComplete register encodingRegister bit field encoding
   WTWBRAWANumSetsAssociativityLineSize
0x032KB0x701FE00A01110x0FF0x10x2
0x148KB0x201FE01200100x0FF0x20x2
0x2512KB0x703FE07A01110x1FF0xF0x2
1024KB0x707FE07A01110x3FF0xF0x2
2048KB0x70FFE07A01110x7FF0xF0x2
0x3-0xF--Reserved

To access the CCSIDR_EL1 in AArch64 state, read the register with:

MRS <Xt>, CCSIDR_EL1; Read Cache Size ID Register

To access the CCSIDR in AArch32 state, read the CP15 register with:

MRC p15, 1, <Rt>, c0, c0, 0; Read Cache Size ID Register
Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914