4.4.27. Security registers

Table 4.109 shows the 32-bit wide Security registers in AArch32 state.

Table 4.109. Security registers

SCRc10c10RW0x00000000Secure Configuration Register
SDER  1RW0x00000000Secure Debug Enable Register [a]
NSACR  2RW0x00000000Non-secure Access Control Register
SDCR  c31RW0x00000000Secure Debug Configuration Register
VBARc120c00RW0x00000000[b]Vector Base Address Register [a]
MVBAR  1RWUNKMonitor Vector Base Address Register [a]
ISR c10ROUNKInterrupt Status Register [a]

[a] See the ARM® Architecture Reference Manual ARMv8 for more information.

[b] The reset value is 0x00000000 for the Secure copy of the register. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.

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