4.3.46. Translation Table Base Register 1, EL1

The TTBR1_EL1 characteristics are:

Purpose

Holds the base address of translation table 1, and information about the memory it occupies. This is one of the translation tables for the stage 1 translation of memory accesses at EL0 and EL1. This is one of the translation tables for the stage 1 translation of memory accesses at EL1 if the highest Exception level is in AArch64 state.

Usage constraints

The TTBR1_EL1 is used in conjunction with TCR_EL1.

The accessibility to the TTBR1_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RWRWRWRWRW
Configurations

TTBR1_EL1 is architecturally mapped to the Non-secure AArch32 register TTBR1.

Attributes

See the register summary in Table 4.3.

Figure 4.42 shows the TTBR1_EL1 bit assignments.

Figure 4.42. TTBR1_EL1 bit assignments

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Table 4.58 shows the TTBR0_EL1 bit assignments.

Table 4.58. TTBR1_EL1 bit assignments

BitsNameFunction
[63:48]ASID

An ASID for the translation table base address.

The TCR_EL1.A1 field selects either the TTBR0.ASID or the TTBR1.ASID.

The TCR_EL1.AS bit selects whether all 16-bits [63:48] or the lower 8-bits [55:48] indicate the current ASID.

[47:10]BADDR

Translation table base address. Defining the translation table base address width.

[9:0]-

Reserved, res0.


To access the TTBR0_EL1 in AArch64 state, read or write the register with:

MRS <Xt>, TTBR1_EL1; Read EL1 Translation Table Base Register 1
MSR TTBR1_EL1, <Xt>; Write EL1 Translation Table Base Register 1
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