4.4.31. Implementation defined registers

Table 4.112 shows the implementation defined registers in AArch32 state. These registers provide test features and any required configuration options specific to the Cortex-A57 MPCore multiprocessor.

Table 4.112. Implementation defined registers

NameCRnop1CRmop2TypeResetWidthDescription
AIDRc01c07-0x0000000032-bitAuxiliary ID Register. See Auxiliary ID Register, EL1.
ACTLRc10c01-0x0000000032-bitAuxiliary Control Register. See Auxiliary Control Register, EL3.
HACTLR4c01RW0x0000000032-bitHyp Auxiliary Control Register. See Auxiliary Control Register, EL2.
HADFSRc54c10RWUNK32-bitHyp Auxiliary Data Fault Status Register. See Auxiliary Fault Status Register 0, EL2 and Hyp Auxiliary Data Fault Status Register.
HAIFSR  1RWUNK32-bitHyp Auxiliary Instruction Fault Status Register. See Auxiliary Fault Status Register 1, EL2 and Hyp Auxiliary Instruction Fault Status Register.
L2CTLRc91c02RW0x00000000[a]32-bitL2 Control Register. See L2 Control Register, EL1.
L2ECTLR  3RW0x0000000032-bitL2 Extended Control Register. See L2 Extended Control Register, EL1.
AMAIR0c100c30RWUNK32-bitAuxiliary Memory Attribute Indirection Register 0. See Auxiliary Memory Attribute Indirection Register, EL1 and EL3.
AMAIR1  1RWUNK32-bitAuxiliary Memory Attribute Indirection Register 1. See Auxiliary Memory Attribute Indirection Register, EL1 and EL3.
HAMAIR0  0RWUNK32-bitHyp Auxiliary Memory Attribute Indirection Register 0. See Auxiliary Memory Attribute Indirection Register, EL2.
HAMAIR1  1RWUNK32-bitHyp Auxiliary Memory Attribute Indirection Register 1. See Auxiliary Memory Attribute Indirection Register, EL2.
IL1DATA0c150c00RWUNK32-bitInstruction L1 Data n Register, EL1.
IL1DATA1  1
IL1DATA2  2
IL1DATA3  3
DL1DATA0  c10RWUNK32-bitData L1 Data n Register, EL1.
DL1DATA1  1
DL1DATA2  2
DL1DATA3  3
DL1DATA4  4
RAMINDEX  c40WO-32-bitRAM Index operation.
L2ACTLR 1c00RW0x00000010[b]32-bitL2 Auxiliary Control Register. See L2 Auxiliary Control Register, EL1.
CBAR 4c00RO-[c]32-bitConfiguration Base Address Register.
CPUACTLR-0c15-RW-[d]64-bitCPU Auxiliary Control Register. See CPU Auxiliary Control Register, EL1.
CPUECTLR-1-RW-[e]64-bitCPU Extended Control Register. See CPU Extended Control Register, EL1.
CPUMERRSR-2-RW-[f]64-bitCPU Memory Error Syndrome Register. See CPU Memory Error Syndrome Register, EL1.
L2MERRSR-3-RW-[f]64-bitL2 Memory Error Syndrome Register. See L2 Memory Error Syndrome Register, EL1.

[a] The reset value depends on the processor implementation and the state of the L2RSTDISABLE signal.

[b] The reset value is 0x00000010 for an ACE interface and 0x00004018 for a CHI interface.

[c] The reset value depends on the primary input, PERIPHBASE[43:18].

[d] The reset value is zero.

[e] The reset value is 0x0000 001B 0000 0000.

[f] The reset value for bits[63,47:40,39:32,31] is zero.


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