4.3.17. AArch32 Instruction Set Attribute Register 5, EL1

The ID_ISAR5_EL1 characteristics are:

Purpose

Provides information about the instruction sets that the processor implements.

Note

  • The optional Cryptography engine is not included in the base product of the processor. ARM requires licensees to have contractual rights to obtain the Cortex-A57 Cryptography engine.

  • The SHA1, SHA2, and AES fields of ID_ISAR5_EL1 are 0x0 if the Cryptography engine is not included or CRYPTODISABLE is tied HIGH.

Usage constraints

The ID_ISAR5_EL1 must be interpreted with:

  • ID_ISAR0_EL1.

  • ID_ISAR1_EL1.

  • ID_ISAR2_EL1.

  • ID_ISAR3_EL1.

  • ID_ISAR4_EL1.

The accessibility to the ID_ISAR5_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

The ID_ISAR5_EL1 is:

  • Common to Secure and Non-secure states.

  • Architecturally mapped to the AArch32 ID_ISAR5 register.

Attributes

See the register summary in Table 4.1.

Figure 4.16 shows the ID_ISAR5_EL1 bit assignments.

Figure 4.16. ID_ISAR5_EL1 bit assignments

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Table 4.31 shows the ID_ISAR5_EL1 bit assignments.

Table 4.31. ID_ISAR5_EL1 bit assignments

BitsNameFunction
[31:20]-

Reserved, res0.

[19:16]CRC32Returns 0x1 to indicate that CRC32 instructions are implemented in AArch32 state.
[15:12]SHA2

Indicates whether SHA2 instructions are implemented in AArch32 state. The possible values are:

0x0

SHA2 instructions are not implemented in AArch32 state.

0x1

SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 instructions are implemented.

All other values are reserved.

[11:8]SHA1

Indicates whether SHA1 instructions are implemented in AArch32 state. The possible values are:

0x0

SHA1 instructions are not implemented in AArch32 state.

0x1

SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions are implemented.

All other values are reserved.

[7:4]AES

Indicates whether AES instructions are implemented in AArch32 state. The possible values are:

0x0

AES instructions are not implemented in AArch32 state.

0x2

AESE, AESD, AESMC, AESIMC, and PMULL/PMULL2 instructions operating on 64-bit data.

All other values are reserved.

[3:0]SEVLReturns 0x1 to indicate that the SEVL instruction is implemented in AArch32 state.

To access the ID_ISAR5_EL1 in AArch64 state, read the register with:

MRS <Xt>, ID_ISAR5_EL1; Read AArch32 Instruction Set Attribute Register 5

To access the ID_ISAR5 in AArch32 state, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c2, 5; Read AArch32 Instruction Set Attribute Register 5
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