4.4.19. Virtual memory control registers

Table 4.100 shows the Virtual memory control registers in AArch32 state.

Table 4.100. Virtual memory control registers

NameCRnop1CRmop2TypeResetWidthDescription
SCTLRc10c00RW0x00C50838[a]32-bitSystem Control Register.
HSCTLRc14c00RW0x30C5083832-bitHyp System Control Register. [b]
TTBR0c20c00RWUNK32-bitTranslation Table Base Register 0. [b]
-0c2-64-bit
TTBR1c20c01RWUNK32-bitTranslation Table Base Register 1. [b]
-1c2-64-bit
TTBCRc20c02RW0x00000000[c]32-bitTranslation Table Base Control Register.
HTCRc24c02RWUNK32-bitHyp Translation Control Register.
VTCR c12RWUNK32-bitVirtualization Translation Control Register. [b]
DACRc30c00RWUNK32-bitDomain Access Control Register. [b]
PRRRc100c20RW0x00098AA432-bitPrimary Region Remap Register.
MAIR0  0RWUNK32-bit Memory Attribute Indirection Register 0.
NMRR  1RW0x44E048E032-bitNormal Memory Remap Register..
MAIR1  1RWUNK32-bit Memory Attribute Indirection Register 1.
AMAIR0  c30RWUNK32-bitAuxiliary Memory Attribute Indirection Register 0. See Auxiliary Memory Attribute Indirection Register, EL1 and EL3.
AMAIR1  1RWUNK32-bitAuxiliary Memory Attribute Indirection Register 1. See Auxiliary Memory Attribute Indirection Register, EL1 and EL3.
HMAIR0 4c20RWUNK32-bitHyp Memory Attribute Indirection Register 0. [b]
HMAIR1  1RWUNK32-bitHyp Memory Attribute Indirection Register 1. [b]
HAMAIR0  c30RWUNK32-bitHyp Auxiliary Memory Attribute Indirection Register 0. See Auxiliary Memory Attribute Indirection Register, EL2.
HAMAIR1  1RWUNK32-bitHyp Auxiliary Memory Attribute Indirection Register 1. See Auxiliary Memory Attribute Indirection Register, EL2.
CONTEXTIDRc130c01RWUNK32-bitContext ID Register. [b]

[a] The reset value depends on primary inputs, CFGTE, CFGEND, and VINITHI. Table 4.100 assumes these signals are LOW.

[b] See the ARM® Architecture Reference Manual ARMv8 for more information.

[c] The reset value is 0x00000000 for the Secure copy of the register. The reset value for the EAE bit of the Non-secure copy of the register is 0x0. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.


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