4.3.8. AArch32 Memory Model Feature Register 0, EL1

The ID_MMFR0_EL1 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support in AArch32.

Usage constraints

The ID_MMFR0_EL1 must be interpreted with:

  • ID_MMFR1_EL1.

  • ID_MMFR2_EL1.

  • ID_MMFR3_EL1.

The accessibility to the ID_MMFR0_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

The ID_MMFR0_EL1 is:

  • Common to Secure and Non-secure states.

  • Architecturally mapped to the AArch32 ID_MMFR0 register.

Attributes

See the register summary in Table 4.1.

Figure 4.7 shows the ID_MMFR0_EL1 bit assignments.

Figure 4.7. ID_MMFR0_EL1 bit assignments

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Table 4.22 shows the ID_MMFR0_EL1 bit assignments.

Table 4.22. ID_MMFR0_EL1 bit assignments

BitsNameFunction
[31:28]InnerShr

Indicates the innermost shareability domain implemented. This value is:

0x1

Processor implements hardware coherency support.

[27:24]FCSE

Indicates support for Fast Context Switch Extension (FCSE). This value is:

0x0

Processor does not support FCSE.

[23:20]AuxReg

Indicates support for Auxiliary registers. This value is:

0x1

Processor supports the ACTLR. See Auxiliary Control Register, EL3.

[19:16]TCM

Indicates support for TCMs and associated DMAs. This value is:

0x0

Processor does not support TCM.

[15:12]ShareLvl

Indicates the number of shareability levels implemented. This value is:

0x1

Processor implements two levels of shareability.

[11:8]OuterShr

Indicates the outermost shareability domain implemented. This value is:

0x1

Processor supports hardware coherency.

[7:4]PMSA

Indicates support for a Protected Memory System Architecture (PMSA). This value is:

0x0

Processor does not support PMSA.

[3:0]VMSA

Indicates support for a Virtual Memory System Architecture (VMSA). This value is:

0x5

Processor supports:

  • VMSAv7, with support for remapping and the Access flag

  • Privileged Execute Never (PXN) bit in the Short-descriptor translation table format

  • The Long-descriptor translation table format.


To access the ID_MMFR0_EL1 in AArch64 state, read the register with:

MRS <Xt>, ID_MMFR0_EL1; Read AArch32 Memory Model Feature Register 0

To access the ID_MMFR0 in AArch32 state, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c1, 4; Read AArch32 Memory Model Feature Register 0
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