4.3.55. Physical Address Register, EL1

The PAR_EL1 characteristics are:

Purpose

The Physical Address returned from an address translation.

Usage constraints

The accessibility of the PAR_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RWRWRWRWRW
Configurations

The architectural mapping of the PAR_EL1 is to the Non-secure AArch32 PAR register. See Physical Address Register for more information.

Attributes

See the register summary in Table 4.7.

Figure 4.48 shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion completes successfully.

Figure 4.48. PAR_EL1 pass bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.65 shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion completes successfully.

Table 4.65.  PAR_EL1 pass bit assignments

BitsNameFunction
[63:60]AttrH

Defines Device memory or Normal memory plus Outer cacheability. Must be used in conjunction with AttrL. The possible values are:

0x0

Device memory, see AttrL.

0x4

Normal memory, Outer Non-cacheable.

0x8

Normal memory, Outer Write-Through Cacheable.

0x9

Normal memory, Outer Write-Through Cacheable, Outer Write-Allocate.

0xA

Normal memory, Outer Write-Through Cacheable, Outer Read-Allocate.

0xB

Normal memory, Outer Write-Through Cacheable, Outer Write-Allocate, Outer Read-Allocate.

0xC

Normal memory, Outer Write-Back Cacheable.

0xD

Normal memory, Outer Write-Back Cacheable, Outer Write-Allocate.

0xE

Normal memory, Outer Write-Back Cacheable, Outer Read-Allocate.

0xF

Normal memory, Outer Write-Back Cacheable, Outer Write-Allocate, Outer Read-Allocate.

All other values are reserved.

[59:56]AttrL

Defines Device memory or Normal memory plus Inner cacheability. Must be interpreted in conjunction with AttrH. The possible values are:

0x0

Device-nGnRnE memory if AttrH is 0x0. Otherwise this value is reserved.

0x4

Device memory if AttrH is 0x0. Otherwise, Normal memory, Inner Non-cacheable.

0x8

Reserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Through Cacheable.

0x9

Reserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Through Cacheable, Inner Write-Allocate.

0xA

Reserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Through Cacheable, Inner Read-Allocate.

0xB

Reserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Through Cacheable, Inner Write-Allocate, Inner Read-Allocate.

0xC

Reserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Back Cacheable.

0xD

Reserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Back Cacheable, Inner Write-Allocate.

0xE

Reserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Back Cacheable, Inner Read-Allocate.

0xF

Reserved if AttrH is 0x0. Otherwise, Normal memory, Inner Write-Through Cacheable, Inner Write-Allocate, Inner Read-Allocate.

All other values are reserved.

[55:44]-Reserved, res0.
[43:12]PAPhysical address. The Physical Address corresponding to the supplied Virtual Address. Returns address bits[31:12].
[11]-Reserved, res1.
[10]-Reserved, res0.
[9]NS

Non-secure. The NS attribute for a translation table entry read from Secure state.

This bit is unknown for a translation table entry from Non-secure state.

[8:7]SHA

Shareability attribute for the Physical Address returned from a translation table entry. The values are:

0b00

Non-shareable.

0b01

Reserved.

0b10

Outer Shareable.

0b11

Inner Shareable.

Note

The SHA bit takes the value of 0b10 for:

  • Any type of device memory.

  • Normal memory with both Inner Non-cacheable and Outer-cacheable attributes.

[6:1]-Reserved, res0.
[0]F

Pass/Fail bit. Indicates whether the conversion completed successfully. This value is:

0

Virtual Address to Physical Address conversion completed successfully.


Figure 4.49 shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion aborts.

Figure 4.49. PAR_EL1 fail bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.66 shows the PAR_EL1 bit assignments when the Virtual Address to Physical Address conversion aborts.

Table 4.66.  PAR_EL1 fail bit assignments

BitsNameFunction
[63:12]-

Reserved, res0.

[11]-Reserved, res1.
[10]-Reserved, res0.
[9]S

Stage of fault. Indicates the state where the translation aborted. The values are:

0

Translation aborted because of a fault in stage 1 translation.

1

Translation aborted because of a fault in stage 2 translation.

[8]PTW

Indicates a stage 2 fault during a stage 1 table walk. The values are:

0

No stage 2 fault during a stage 1 table walk.

1

Translation aborted because of a stage 2 fault during a stage 1 table walk.

[7]-Reserved, res0.
[6:1]FST

Fault status code, as shown in the Data Abort ESR encoding. See the ARM® Architecture Reference Manual ARMv8 for more information.

[0]F

Pass/Fail bit. Indicates whether the conversion completed successfully. The value is:

1

Virtual Address to Physical Address conversion aborted.


To access the PAR_EL1 in AArch64 state, read or write the register with:

MRS <Xt>, PAR_EL1; Read EL1 Physical Address Register
MSR PAR_EL1, <Xt>; Write EL1 Physical Address Register
Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914