4.3.37. Hyp Auxiliary Configuration Register

The processor does not implement HACR_EL2 in AArch64 state. This register is res0 in EL2 and EL3.

The processor does not implement HACR in AArch32 state. This register is res0 in Hyp mode and in Monitor mode when SCR.NS is 1.

Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914