4.3.67. CPU Extended Control Register, EL1

The CPUECTLR_EL1 characteristics are:

Purpose

Provides additional implementation defined configuration and control options for the processor.

Usage constraints

The accessibility to the CPUECTLR_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RW[a]RW[a]RW[b]RWRW

[a] Write access if ACTLR_EL3.CPUECTLR is 1 and ACTLR_EL2.CPUECTLR is 1, or ACTLR_EL3.CPUECTLR is 1 and SCR.NS is 0.

[b] Write access if ACTLR_EL3.CPUECTLR is 1.

The CPUECTLR_EL1 can be written dynamically.

Configurations

The CPUECTLR_EL1 is:

  • Common to the Secure and Non-secure states.

  • A 64-bit read/write register.

  • Architecturally mapped to the AArch32 CPUECTLR register.

Attributes

See the register summary in Table 4.15.

Figure 4.75 shows the CPUECTLR_EL1 bit assignments.

Figure 4.75. CPUECTLR_EL1 bit assignments

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Table 4.77 shows the CPUECTLR_EL1 bit assignments.

Table 4.77. CPUECTLR_EL1 bit assignments

BitsNameFunction
[63:39]-

Reserved, res0.

[38]Disable table walk descriptor access prefetch

Disables table walk descriptor access prefetch. The possible values are:

0

Enables table walk descriptor access prefetch. This is the reset value.

1

Disables table walk descriptor access prefetch.

[37]-

Reserved, res0.

[36:35]L2 instruction fetch prefetch distance

Indicates the L2 instruction fetch prefetch distance. It is the number of requests by which the prefetcher is ahead of the demand request stream. It also specifies the maximum number of prefetch requests generated on a demand miss. The possible values are:

0b00

0 requests, disables instruction prefetch.

0b01

1 request.

0b10

2 requests.

0b11

3 requests. This is the reset value.

[34]-

Reserved, res0.

[33:32]L2 load/store data prefetch distance

Indicates the L2 load/store data prefetch distance. It is the number of requests by which the prefetcher is ahead of the demand request stream. It also specifies the maximum number of prefetch requests generated on a demand miss. The possible values are:

0b00

0 requests, disables load/store data prefetch.

0b01

2 requests.

0b10

4 requests.

0b11

8 requests. This is the reset value.

[31:7]-

Reserved, res0.

[6]

SMPEN

Enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster.

You must set this bit before enabling the caches and MMU, or performing any cache and TLB maintenance operations.

You must clear this bit during a processor power down sequence. See Power management.

The possible values are:

0

Disables receiving of instruction cache and TLB maintenance operations. This is the reset value.

1

Enables receiving of instruction cache and TLB maintenance operations.

Note

  • Any processor instruction cache and TLB maintenance operations can execute the request, regardless of the value of the SMPEN bit.

  • This bit has no impact on data cache maintenance operations.

  • In the Cortex-A57 MPCore processor, the L1 data cache and L2 cache are always coherent, for shared or non-shared data, regardless of the value of the SMPEN bit.

[5:3]-

Reserved, res0.

[2:0]Processor dynamic retention control

Processor dynamic retention control. The possible values are:

0b000

Processor dynamic retention disabled. This is the reset value.

0b001

2 Generic Timer ticks required before retention entry.

0b010

8 Generic Timer ticks required before retention entry.

0b011

32 Generic Timer ticks required before retention entry.

0b100

64 Generic Timer ticks required before retention entry.

0b101

128 Generic Timer ticks required before retention entry.

0b110

256 Generic Timer ticks required before retention entry.

0b111

512 Generic Timer ticks required before retention entry.

All other values are reserved.


To access the CPUECTLR_EL1 in AArch64 state, read or write the register with:

MRS <Xt>, S3_1_c15_c2_1; Read EL1 CPU Extended Control Register
MSR S3_1_c15_c2_1, <Xt>; Write EL1 CPU Extended Control Register

To access the CPUECTLR in AArch32 state, read or write the CP15 register with:

MRRC p15, 1, <Rt>, <Rt2>, c15; Read CPU Extended Control Register
MCRR p15, 1, <Rt>, <Rt2>, c15; Write CPU Extended Control Register
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