4.3.10. AArch32 Memory Model Feature Register 2, EL1

The ID_MMFR2_EL1 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support of the processor in AArch32.

Usage constraints

The ID_MMFR2_EL1 must be interpreted with:

  • ID_MMFR0_EL1.

  • ID_MMFR1_EL1.

  • ID_MMFR3_EL1.

The accessibility to the ID_MMFR2_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

The ID_MMFR2_EL1 is:

  • Common to Secure and Non-secure states.

  • Architecturally mapped to the AArch32 ID_MMFR2 register.

Attributes

See the register summary in Table 4.1.

Figure 4.9 shows the ID_MMFR2_EL1 bit assignments.

Figure 4.9. ID_MMFR2_EL1 bit assignments

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Table 4.24 shows the ID_MMFR2_EL1 bit assignments.

Table 4.24. ID_MMFR2_EL1 bit assignments

BitsNameFunction
[31:28]HWAccFlg

Indicates support for Hardware Access flag. This value is:

0x0

Not supported.

[27:24]WFIStall

Indicates support for Wait For Interrupt (WFI) stalling. This value is:

0x1

Processor supports WFI stalling.

[23:20]MemBarr

Indicates the supported CP15 memory barrier operations. This value is:

0x2

Processor supports:

  • Data Synchronization Barrier (DSB).

  • Instruction Synchronization Barrier (ISB).

  • Data Memory Barrier (DMB).

ARM deprecates the use of these CP15 operations. Instead, use the DMB, DSB, and ISB barrier instructions.

[19:16]UniTLB

Indicates the supported TLB maintenance operations. This value is:

0x6

Processor supports:

  • Invalidate all entries in the TLB.

  • Invalidate TLB entry by VA.

  • Invalidate TLB entries by ASID match.

  • Invalidate instruction TLB and data TLB entries by VA All ASID. This is a shared unified TLB operation.

  • Invalidate Hyp mode unified TLB entry by VA.

  • Invalidate entire Non-secure PL1 and PL0 unified TLB.

  • Invalidate entire Hyp mode unified TLB.

  • Invalidate TLB entry by VA, Last Level.

  • Invalidate TLB entry by VA and ASID, Last Level.

  • Invalidate Stage 2 TLB only by IPA.

  • Invalidate Stage 2 TLB only by IPA, Last Level.

[15:12]HvdTLB

Indicates support for Harvard TLB maintenance operations. This value is:

0x0

Not supported.

[11:8]L1HvdRng

Indicates support for Harvard L1 cache maintenance range operations. This value is:

0x0

Not supported.

[7:4]L1HvdBG

Indicates support for Harvard L1 cache background fetch operations. This value is:

0x0

Not supported.

[3:0]L1HvdFG

Indicates support for Harvard L1 cache foreground fetch operations. This value is:

0x0

Not supported.


To access the ID_MMFR2_EL1 in AArch64 state, read the register with:

MRS <Xt>, ID_MMFR2_EL1; Read AArch32 Memory Model Feature Register 2

To access the ID_MMFR2 in AArch32 state, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c1, 6; Read AArch32 Memory Model Feature Register 2
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