11.7.1. Performance Monitors Control Register, EL0

The PMCR_EL0 characteristics are:


Configures and controls the counters.

Usage constraints

The external accessibility to the PMCR_EL0 by condition code is:


Table 11.1 describes the access conditions.


The PMCR_EL0 is Common to Secure and Non-secure states and architecturally mapped to:

  • The AArch32 PMCR register.

  • The external PMCR_EL0 register.


See the register summary in Table 11.7.

Figure 11.4 shows the PMCR_EL0 bit assignments for a memory-mapped access.

Figure 11.4. PMCR_EL0 bit assignments, memory-mapped view

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Table 11.8 shows the PMCR_EL0 bit assignments for a memory-mapped access.

Table 11.8. PMCR_EL0 bit assignments, memory-mapped view


Reserved, res0.

[6]LCThe function of these bits is the same as when a System register access occurs. See Table 11.4 for a description of these bits.

The PMCR_EL0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xE04.

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