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Home > Advanced SIMD and Floating-point > AArch64 register descriptions > Media and VFP Feature Register 2, EL1 |
The MVFR2_EL1 characteristics are:
The MVFR2_EL1 must be interpreted with the MVFR0_EL1 and the MVFR1_EL1 to describe the features provided by the Advanced SIMD and FP functions.
The accessibility to the MVFR2_EL1 in AArch64 state by Exception level is:
EL0 | EL1(NS) | EL1(S) | EL2 | EL3(SCR.NS = 1) | EL3(SCR.NS = 0) |
---|---|---|---|---|---|
- | RO | RO | RO | RO | RO |
The accessibility to the MVFR2 in AArch32 state by Exception level is:
EL0 | EL1(NS) | EL1(S) | EL2 | EL3(SCR.NS = 1) | EL3(SCR.NS = 0) |
---|---|---|---|---|---|
- | Config | RO | Config | Config | RO |
The MVFR2_EL1 is:
Common to Secure and Non-secure states.
Architecturally mapped to AArch32 MVFR2 register.
See the register summary in Table 14.2.
Figure 14.5 shows the MVFR2_EL1 bit assignments.
Table 14.7 shows the MVFR2_EL1 bit assignments.
Table 14.7. MVFR2_EL1 bit assignments
Bits | Name | Function |
---|---|---|
[31:8] | - | Reserved, res0. |
[7:4] | FPMisc | Floating-point miscellaneous features supported. This value is:
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[3:0] | SIMDMisc | Advanced SIMD miscellaneous features supported. This value is:
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To access the MVFR2_EL1 register, see Programmers model for Advanced SIMD and Floating-point.