14.4.5. Media and VFP Feature Register 2, EL1

The MVFR2_EL1 characteristics are:

Purpose

The MVFR2_EL1 must be interpreted with the MVFR0_EL1 and the MVFR1_EL1 to describe the features provided by the Advanced SIMD and FP functions.

Usage constraints

The accessibility to the MVFR2_EL1 in AArch64 state by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO

The accessibility to the MVFR2 in AArch32 state by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-ConfigROConfigConfigRO
Configurations

The MVFR2_EL1 is:

  • Common to Secure and Non-secure states.

  • Architecturally mapped to AArch32 MVFR2 register.

Attributes

See the register summary in Table 14.2.

Figure 14.5 shows the MVFR2_EL1 bit assignments.

Figure 14.5. MVFR2_EL1 bit assignments

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Table 14.7 shows the MVFR2_EL1 bit assignments.

Table 14.7. MVFR2_EL1 bit assignments 

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]FPMisc

Floating-point miscellaneous features supported. This value is:

0x0100

Includes support for the following features:

  • Floating-point selection.

  • Floating-point Conversion to Integer with Directed Rounding modes.

  • Floating-point Round to Integral floating-point.

  • Floating-point MaxNum and MinNum.

[3:0]SIMDMisc

Advanced SIMD miscellaneous features supported. This value is:

0x011

Includes support for the following features:

  • Floating-point Conversion to Integer with Directed Rounding modes.

  • Floating-point Round to Integral floating-point.

  • Floating-point MaxNum and MinNum.


To access the MVFR2_EL1 register, see Programmers model for Advanced SIMD and Floating-point.

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