4.4.18. CPUID registers

Table 4.99 shows the CPUID registers in AArch32 state.

Table 4.99. CPUID registers

NameCRnop1CRmop2TypeResetDescription
ID_PFR0c00c10RO0x00000131Processor Feature Register 0. See AArch32 Processor Feature Register 0, EL1.
ID_PFR1  1RO0x00011011[a]Processor Feature Register 1. See AArch32 Processor Feature Register 1, EL1.
ID_DFR0  2RO0x03010066Debug Feature Register 0. See AArch32 Debug Feature Register 0, EL1.
ID_AFR0  3RO0x00000000Auxiliary Feature Register 0. See AArch32 Auxiliary Feature Register 0, EL1.
ID_MMFR0  4RO0x10101105Memory Model Feature Register 0. See AArch32 Memory Model Feature Register 0, EL1.
ID_MMFR1  5RO0x40000000Memory Model Feature Register 1. See AArch32 Memory Model Feature Register 1, EL1.
ID_MMFR2  6RO0x01260000Memory Model Feature Register 2. See AArch32 Memory Model Feature Register 2, EL1.
ID_MMFR3  7RO0x02102211Memory Model Feature Register 3. See AArch32 Memory Model Feature Register 3, EL1.
ID_ISAR0  c20RO0x02101110Instruction Set Attribute Register 0. See AArch32 Instruction Set Attribute Register 0, EL1.
ID_ISAR1  1RO0x13112111Instruction Set Attribute Register 1. See AArch32 Instruction Set Attribute Register 1, EL1.
ID_ISAR2  2RO0x21232042Instruction Set Attribute Register 2. See AArch32 Instruction Set Attribute Register 2, EL1.
ID_ISAR3  3RO0x01112131Instruction Set Attribute Register 3. See AArch32 Instruction Set Attribute Register 3, EL1.
ID_ISAR4  4RO0x00011142Instruction Set Attribute Register 4. See AArch32 Instruction Set Attribute Register 4, EL1.
ID_ISAR5  5RO0x00000001[b]Instruction Set Attribute Register 5. See AArch32 Instruction Set Attribute Register 5, EL1.

[a] The reset value depends on the primary input GICCDISABLE. The value shown assumes the GICCDISABLE signal is tied HIGH.

[b] The reset value is 0x00001121 if the Cryptography engine is implemented.


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