14.3. AArch64 register summary

Table 14.2 gives a summary of the Cortex-A57 MPCore multiprocessor Advanced SIMD and Floating-point System registers in AArch64 state. All AArch64 registers are 32-bit wide.

Table 14.2. AArch64 Advanced SIMD and Floating-point System registers

FPCRRW0x00000000See Floating-point Control Register
FPSRRW0x00000000See Floating-point Status Register
MVFR0_EL1RO0x10110222See Media and VFP Feature Register 0, EL1
MVFR1_EL1RO0x12111111See Media and VFP Feature Register 1, EL1
MVFR2_EL1RW0x00000043See Media and VFP Feature Register 2, EL1
FPEXC32_EL2RW0x00000700See Floating-point Exception Control Register 32, EL2

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