4.3.12. AArch32 Instruction Set Attribute Register 0, EL1

The ID_ISAR0_EL1 characteristics are:

Purpose

Provides information about the instruction set that the processor supports in AArch32.

Usage constraints

The ID_ISAR0_EL1 must be interpreted with:

  • ID_ISAR1_EL1.

  • ID_ISAR2_EL1.

  • ID_ISAR3_EL1.

  • ID_ISAR4_EL1.

  • ID_ISAR5_EL1.

The accessibility to the ID_ISAR0_EL1 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

The ID_ISAR0_EL1 is:

  • Common to Secure and Non-secure states.

  • Architecturally mapped to the AArch32 ID_ISAR0 register.

Attributes

See the register summary in Table 4.1.

Figure 4.11 shows the ID_ISAR0_EL1 bit assignments.

Figure 4.11. ID_ISAR0_EL1 bit assignments

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Table 4.26 shows the ID_ISAR0_EL1 bit assignments.

Table 4.26. ID_ISAR0_EL1 bit assignments

BitsNameFunction
[31:28]-

Reserved, res0.

[27:24]Divide

Returns 0x2 to indicate the processor implements the following divide instructions:

  • SDIV and UDIV in the T32 instruction set.

  • SDIV and UDIV in the A32 instruction set.

[23:20]Debug

Returns 0x1 to indicate the processor implements the BKPT debug instruction.

[19:16]Coproc

Returns 0x0 to indicate the processor implements no coprocessor instructions, except for separately attributed architectures including CP15, CP14, and Advanced SIMD and FP.

[15:12]CmpBranch

Returns 0x1 to indicate the processor implements the CBNZ and CBZ, Compare and Branch, instructions in the T32 instruction set.

[11:8]Bitfield

Returns 0x1 to indicate the processor implements the BFC, BFI, SBFX, and UBFX, bit field instructions.

[7:4]BitCount

Returns 0x1 to indicate the processor implements the CLZ bit counting instruction.

[3:0]Swap

Returns 0x0 to indicate the processor implements no swap instructions in the A32 instruction set.


To access the ID_ISAR0_EL1 in AArch64 state, read the register with:

MRS <Xt>, ID_ISAR0_EL1; Read AArch32 Instruction Set Attribute Register 0

To access the ID_ISAR0 in AArch32 state, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c2, 0; Read AArch32 Instruction Set Attribute Register 0
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