4.3.60. Reset Vector Base Address, EL3

The RVBAR_EL3 characteristics are:

Purpose

Defines the address that execution starts from after reset when executing in the AArch64 state.

RVBAR_EL3 is part of the reset management registers functional group.

Usage constraints

The accessibility of the RVBAR_EL3 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
----RORO
Configurations

Only implemented if the highest Exception level implemented is EL3.

Attributes

See the register summary in Table 4.11.

Figure 4.52 shows the RVBAR_EL3 bit assignments.

Figure 4.52. RVBAR_EL3 bit assignments

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Table 4.69 shows the RVBAR_EL3 bit assignments.

Table 4.69.  RVBAR_EL3 bit assignments

BitsNameFunction
[63:44]-Reserved, res0.
[43:2]Reset Vector Base Address

Reset Vector Base Address when executing in the AArch64 state. The reset address for processor n is set by the RVBARADDRn[43:2] input signals.

[1:0]-Reserved, res0.

To access the RVBAR_EL3 in AArch64 state, read the register with:

MRS <Xt>, RVBAR_EL3; Read RVBAR_EL3 Reset Vector Base Address Register
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