4.3.43. Virtualization Translation Control Register, EL2

The VTCR_EL2 characteristics are:

Purpose

Controls the translation table walks required for the stage 2 translation of memory accesses from Non-secure EL0 and EL1, and holds cacheability and shareability information for the accesses.

Usage constraints

The accessibility to the VTCR_EL2 by Exception level is:

EL0EL1(NS)EL1(S)EL2EL3(SCR.NS = 1)EL3(SCR.NS = 0)
---RWRWRW
Configurations

The VTCR_EL2 is:

  • A32-bit register in AArch64 state.

  • Architecturally mapped to the AArch32 VTCR register.

Attributes

See the register summary in Table 4.3.

Figure 4.39 shows the VTCR_EL2 bit assignments.

Figure 4.39. VTCR_EL2 bit assignments

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Table 4.55 shows the VTCR_EL2 bit assignments.

Table 4.55. VTCR_EL2 bit assignments

BitsNameFunction
[31]-

Reserved, res1.

[30:19]-

Reserved, res0.

[18:16]PS

Physical Address Size. The possible values are:

0b000

32-bit, 4GBytes.

0b001

36-bit, 64GBytes.

0b010

40-bit, 1TByte.

0b011

42-bit, 4TBytes.

0b100

44-bit, 16TBytes.

0b101

48-bit, 256TBytes.

All other values are reserved.

[15]-

Reserved, res0.

[14]TG0

Granule size for the corresponding TTBR0_ELx.

0

4KB.

1

64KB.

[13:12]SH0

Shareability attribute for memory associated with translation table walks using TTBR0:

0b00

Non-shareable.

0b01

Reserved.

0b11

Outer Shareable.

0b11

Inner Shareable.

[11:10]ORGN0

Outer cacheability attribute for memory associated with translation table walks using TTBR0.

0b00

Normal memory, Outer Non-cacheable.

0b01

Normal memory, Outer Write-Back Write-Allocate Cacheable.

0b11

Normal memory, Outer Write-Through Cacheable.

0b11

Normal memory, Outer Write-Back no Write-Allocate Cacheable.

[9:8]IRGN0

Inner cacheability attribute for memory associated with translation table walks using TTBR0.

0b00

Normal memory, Inner Non-cacheable.

0b01

Normal memory, Inner Write-Back Write-Allocate Cacheable.

0b11

Normal memory, Inner Write-Through Cacheable.

0b11

Normal memory, Inner Write-Back no Write-Allocate Cacheable.

[7:6]SL0Starting level of the VTCR_EL2 addressed region.
[5:0]T0SZ

The size offset of the memory region addressed by TTBR0. The region size is 2(32-T0SZ) bytes.


To access the VTCR_EL2 in AArch64 state, read or write the register with:

MRS <Xt>, VTCR_EL2; Read EL2 Virtualization Translation Control Register
MSR VTCR_EL2, <Xt>; Write EL2 Virtualization Translation Control Register
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