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Home > System Control > AArch64 register descriptions > Translation Control Register, EL2 |
The TCR_EL2 characteristics are:
Controls translation table walks required for stage 1 translation of a memory access from EL2 and holds cacheability and shareability information.
The accessibility of the TCR_EL2 by Exception level is:
EL0 | EL1(NS) | EL1(S) | EL2 | EL3(SCR.NS = 1) | EL3(SCR.NS = 0) |
---|---|---|---|---|---|
- | - | - | RW | RW | RW |
The TCR_EL2 is architecturally mapped to the AArch32 HCTR register. See Hyp Translation Control Register for more information.
See the register summary in Table 4.3.
Figure 4.38 shows the TCR_EL2 bit assignments.
Table 4.54 shows the TCR_EL2 bit assignments.
Table 4.54. TCR_EL2 bit assignments
Bits | Name | Function |
---|---|---|
[31] | - | Reserved, res1. |
[30:24] | - | Reserved, res0. |
[23] | - | Reserved, res1. |
[22:21] | - | Reserved, res0. |
[20] | TBI | Top Byte Ignored. Indicates whether the top byte of the input address is used for address match. The values are:
|
[19] | - | Reserved, res0. |
[18:16] | PS | Physical Address size. The possible values are:
All other values are reserved. |
[15] | - | Reserved, res0. |
[14] | TG0 | TTBR0_EL2 granule size. The values are:
|
[13:12] | SH0 | Shareability attribute for memory associated with translation table walks using TTBR0. The values are:
|
[11:10] | ORGN0 | Outer cacheability attribute for memory associated with translation table walks using TTBR0. The values are:
|
[9:8] | IRGN0 | Inner cacheability attribute for memory associated with translation table walks using TTBR0. The values are:
|
[7:6] | - | Reserved, res0. |
[5:0] | T0SZ | Size offset of the memory region addressed by TTBR0. The region size is 2(32-TSIZE) bytes. |
To access the TCR_EL2 in AArch64 state, read or write the register with:
MRS <Xt>, TCR_EL2; Read EL2 Translation Control Register MSR TCR_EL2, <Xt>; Write EL2 Translation Control Register