ARM Cortex-A57 MPCore Processor Technical Reference Manual: 4.3.42. Translation Control Register, EL2

4.3.42. Translation Control Register, EL2

The TCR_EL2 characteristics are:

Purpose

Controls translation table walks required for stage 1 translation of a memory access from EL2 and holds cacheability and shareability information.

Usage constraints

The accessibility of the TCR_EL2 by Exception level is:

EL0	EL1(NS)	EL1(S)	EL2	EL3(SCR.NS = 1)	EL3(SCR.NS = 0)
-	-	-	RW	RW	RW

Configurations

The TCR_EL2 is architecturally mapped to the AArch32 HCTR register. See Hyp Translation Control Register for more information.

Attributes

See the register summary in Table 4.3.

Figure 4.38 shows the TCR_EL2 bit assignments.

Figure 4.38. TCR_EL2 bit assignments

Table 4.54 shows the TCR_EL2 bit assignments.

Table 4.54. TCR_EL2 bit assignments

Bits	Name	Function
[31]	-	Reserved, res1.
[30:24]	-	Reserved, res0.
[23]	-	Reserved, res1.
[22:21]	-	Reserved, res0.
[20]	TBI	Top Byte Ignored. Indicates whether the top byte of the input address is used for address match. The values are: 0 Top byte used in the address calculation. 1 Top byte ignored in the address calculation.
[19]	-	Reserved, res0.
[18:16]	PS	Physical Address size. The possible values are: `0b000` 32-bit, 4GBytes. `0b001` 36-bit, 64GBytes. `0b010` 40-bit, 1TByte. `0b011` 42-bit, 4TBytes. `0b100` 44-bit, 16TBytes. `0b101` 48-bit, 256TBytes. All other values are reserved.
[15]	-	Reserved, res0.
[14]	TG0	TTBR0_EL2 granule size. The values are: 0 4KByte. 1 64KByte.
[13:12]	SH0	Shareability attribute for memory associated with translation table walks using TTBR0. The values are: `0b00` Non-shareable. `0b01` Reserved. `0b10` Outer Shareable. `0b11` Inner Shareable.
[11:10]	ORGN0	Outer cacheability attribute for memory associated with translation table walks using TTBR0. The values are: `0b00` Normal memory, Outer Non-cacheable. `0b01` Normal memory, Outer Write-Back Write-Allocate Cacheable. `0b10` Normal memory, Outer Write-Through Cacheable. `0b11` Normal memory, Outer Write-Back no Write-Allocate Cacheable.
[9:8]	IRGN0	Inner cacheability attribute for memory associated with translation table walks using TTBR0. The values are: `0b00` Normal memory, Inner Non-cacheable. `0b01` Normal memory, Inner Write-Back Write-Allocate Cacheable. `0b10` Normal memory, Inner Write-Through Cacheable. `0b11` Normal memory, Inner Write-Back no Write-Allocate Cacheable.
[7:6]	-	Reserved, res0.
[5:0]	T0SZ	Size offset of the memory region addressed by TTBR0. The region size is 2^(32-TSIZE) bytes.

To access the TCR_EL2 in AArch64 state, read or write the register with:

MRS <Xt>, TCR_EL2; Read EL2 Translation Control Register
MSR TCR_EL2, <Xt>; Write EL2 Translation Control Register

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