14.5. AArch32 register summary

Table 14.9 gives a summary of the Advanced SIMD and Floating-point System registers in the Cortex-A57 MPCore multiprocessor when in AArch32 state.

Table 14.9. AArch32 Advanced SIMD and Floating-point System registers


Note

The Floating-point Instruction Registers, FPINST and FPINST2 are not implemented, and any attempt to access them is unpredictable.

See the ARM® Architecture Reference Manual ARMv8 for information about permitted accesses to the Advanced SIMD and Floating-point System registers.

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