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This appendix describes the technical changes between released issues of this book.
Table C.2. Differences between issue A and issue B
Change | Location | Affects |
---|---|---|
Renamed timer events to timer interrupts | Throughout the book | All revisions |
Added configuration requirement when connecting to a CHI interconnect | All revisions | |
Added information about CLREXMONREQ in systems without a global exclusive monitor | All revisions | |
Added information about AINACTS assertion | All revisions | |
Changed or EvictDataUC to WriteEvict | All revisions | |
Added the WFE option | All revisions | |
Updated the step instructions for entering L2 RAMs dynamic retention | All revisions | |
Updated reset value of Main ID Register | r0p1 | |
Updated reset value for ID_ISAR4 | All revisions | |
Updated reset value and footnote for L2ACTLR | All revisions | |
Corrected the reset value of AIDR_EL1 | All revisions | |
Updated reset value of TRCIDR1 | r0p1 | |
Updated the size and the associativity values
for | All revisions | |
Updated the example to read an entry in the instruction side TLB in AArch64 state | All revisions | |
Added footnote about those L2ACTLR_EL1 register bits that are for debugging and characterization only | All revisions | |
Added bits [47] and [38] | All revisions | |
Updated the description of bits [53], [44], [24], and [1] | ||
Added footnote about the bit being for debugging and characterization only to bits [50], [49], [48], [31], and [16], | ||
Added bit[39] | r0p1 | |
Updated the description of CPUECTLR_EL1.SMPEN | All revisions | |
Updated the description of Cluster ID Aff2 | All revisions | |
Added sections related to the CHI protocol | All revisions | |
Added information related to the SLVERR response | All revisions | |
Updated the value for Peripheral ID2 register | r0p1 | |
Updated the information about UNALIGNED_LD_SPEC | All revisions | |
Updated the information about ACINACTM | All revisions | |
Updated the information about AINACTS | All revisions |
Table C.3. Differences between issue B and issue C
Change | Location | Affects |
---|---|---|
Added L2 FEQ20 | r1p0 | |
Added L2 Inclusion PF RAM | r1p0 | |
Updated the product revision information | r1p0 | |
Updated the purpose field of the register characteristics | All revisions | |
Updated the description of CLIDR_EL1.LoUU | All revisions | |
Updated the description of L2ECTLR_EL1.[29] | All revisions | |
Updated the bit ranges for DL1DATA<n> | All revisions | |
Updated the state values for DL1DATA[1:0] | All revisions | |
Updated the description of L2ACTLR_EL1[21:20] | r1p0 | |
Updated the description for CPUECTLR_EL1[36:35] and [33:32] | All revisions | |
Updated the description of fetches | All revisions | |
Updated the description of the L2 cache prefetcher | All revisions | |
Updated the issuing capability information | All revisions | |
Updated the description of BROADCASTCACHEMAINT | All revisions | |
Updated the description of ACE supported transfers | All revisions | |
Updated the description of the GIC memory map | All revisions | |
Updated the description of the interrupt inputs | All revisions | |
Added EDRCR | All revisions | |
Added DBGL1RSTDISABLE | r1p0 | |
Updated the configuration information of all CTI Peripheral Identification Registers | All revisions | |
Updated the number of processors available for tracing | All revisions |
Table C.4. Differences between Issue C and Issue D
Change | Location | Affects |
---|---|---|
Updated reset value of Main ID Register | r1p1 | |
Updated list of ACE supported transfers | All revisions | |
Corrected register bits used to disable L2 prefetches during individual processor powerdown. | Individual processor powerdown | All revisions |