Appendix C. Revisions

This appendix describes the technical changes between released issues of this book.

Table C.1. Issue A

Change

Location

Affects

First release

-

-


Table C.2. Differences between issue A and issue B

Change

Location

Affects

Renamed timer events to timer interrupts

Throughout the book

All revisions

Added configuration requirement when connecting to a CHI interconnect

Implementation options

All revisions

Added information about CLREXMONREQ in systems without a global exclusive monitor

CLREXMON request and acknowledge signaling

All revisions

Added information about AINACTS assertion

All revisions

Changed or EvictDataUC to WriteEvict

All revisions

Added the WFE option

Power modes

All revisions

Updated the step instructions for entering L2 RAMs dynamic retention

L2 RAMs dynamic retention

All revisions

Updated reset value of Main ID Register

r0p1

Updated reset value for ID_ISAR4

All revisions

Updated reset value and footnote for L2ACTLR

All revisions

Corrected the reset value of AIDR_EL1

Table 4.1

All revisions

Updated reset value of TRCIDR1

Table 13.21

r0p1

Updated the size and the associativity values for 0x1

Table 4.37

All revisions

Updated the example to read an entry in the instruction side TLB in AArch64 state

L2 Dirty RAM

All revisions

Added footnote about those L2ACTLR_EL1 register bits that are for debugging and characterization only

Table 4.74

All revisions

Added bits [47] and [38]

CPU Auxiliary Control Register, EL1

All revisions

Updated the description of bits [53], [44], [24], and [1]

Added footnote about the bit being for debugging and characterization only to bits [50], [49], [48], [31], and [16],

Added bit[39]

CPU Auxiliary Control Register, EL1

r0p1

Updated the description of CPUECTLR_EL1.SMPEN

Table 4.77

All revisions

Updated the description of Cluster ID Aff2

Table 4.114

All revisions

Added sections related to the CHI protocol

All revisions

Added information related to the SLVERR response

ACP ARUSER and AWUSER signals

All revisions

Updated the value for Peripheral ID2 register

r0p1

Updated the information about UNALIGNED_LD_SPEC

Table 11.24

All revisions

Updated the information about ACINACTM

Clock and configuration signals

All revisions

Updated the information about AINACTS

Clock and configuration signals

All revisions


Table C.3. Differences between issue B and issue C

Change

Location

Affects

Added L2 FEQ20

r1p0

Added L2 Inclusion PF RAM

r1p0

Updated the product revision information

r1p0

Updated the purpose field of the register characteristics

AArch32 Instruction Set Attribute Register 5, EL1

All revisions

Updated the description of CLIDR_EL1.LoUU

Cache Level ID Register, EL1

All revisions

Updated the description of L2ECTLR_EL1.[29]

L2 Extended Control Register, EL1

All revisions

Updated the bit ranges for DL1DATA<n>

L1-D TLB array

All revisions

Updated the state values for DL1DATA[1:0]

All revisions

Updated the description of L2ACTLR_EL1[21:20]

L2 Auxiliary Control Register, EL1

r1p0

Updated the description for CPUECTLR_EL1[36:35] and [33:32]

CPU Extended Control Register, EL1

All revisions

Updated the description of fetches

Non-cacheable fetching

All revisions

Updated the description of the L2 cache prefetcher

L2 cache prefetcher

All revisions

Updated the issuing capability information

L2 memory interface attributes

All revisions

Updated the description of BROADCASTCACHEMAINT

BROADCASTCACHEMAINT

All revisions

Updated the description of ACE supported transfers

ACE supported transfers

All revisions

Updated the description of the GIC memory map

GIC memory map

All revisions

Updated the description of the interrupt inputs

nIRQ and nVFIQ inputs

All revisions

Added EDRCR

External Debug Reserve Control Register

All revisions

Added DBGL1RSTDISABLE

r1p0

Updated the configuration information of all CTI Peripheral Identification Registers

CTI Component Identification Registers

All revisions

Updated the number of processors available for tracing

ETM trace generation options and resources

All revisions


Table C.4. Differences between Issue C and Issue D

Change

Location

Affects

Updated reset value of Main ID Register

r1p1

Updated list of ACE supported transfers

ACE supported transfers

All revisions

Corrected register bits used to disable L2 prefetches during individual processor powerdown.Individual processor powerdown

All revisions


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