2.3.1. Clocks

The multiprocessor has the following clock inputs:

CLK

This is the main clock of the Cortex-A57 MPCore multiprocessor. All processors, the shared L2 memory system logic, the GIC, and the Generic Timer are clocked with a distributed version of CLK.

PCLKDBG

This is the APB clock that controls the Debug APB, CTI, and CTM logic in the PCLKDBG domain. PCLKDBG is asynchronous to CLK.

The multiprocessor has the following clock enable inputs:

ACLKENM

The AXI master interface is a synchronous AXI interface that can operate at any integer multiple that is equal to or slower than the multiprocessor clock, CLK, using the ACLKENM signal. For example, you can set the CLK to ACLKM frequency ratio to 1:1, 2:1, or 3:1, where ACLKM is the AXI master clock. ACLKENM asserts one CLK cycle prior to the rising edge of ACLKM. The CLK to ACLKM frequency ratio can be changed dynamically using ACLKENM.

Figure 2.2 shows a timing example of ACLKENM that changes the CLK to ACLKM frequency ratio from 3:1 to 1:1.

Figure 2.2. ACLKENM with CLK:ACLKM ratio changing from 3:1 to 1:1

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Note

  • Figure 2.2 shows the timing relationship between the AXI master clock, ACLKM and ACLKENM, where ACLKENM asserts one CLK cycle before the rising edge of ACLKM. It is important that the relationship between ACLKM and ACLKENM is maintained.

  • The input signal ACLKENM exists in the multiprocessor if it is configured to include the ACE interface.

SCLKEN

The CHI interface is a synchronous interface that can operate at any integer multiple that is equal to or slower than the multiprocessor clock, CLK, using the SCLKEN signal. For example, you can set the CLK to SCLK frequency ratio to 1:1, 2:1, or 3:1, where SCLK is the CHI clock. SCLKEN asserts one CLK cycle prior to the rising edge of SCLK. The CLK to SCLK frequency ratio can be changed dynamically using SCLKEN.

Figure 2.3 shows a timing example of SCLKEN that changes the CLK to SCLK frequency ratio from 3:1 to 1:1.

Figure 2.3. SCLKEN with CLK:SCLK ratio changing from 3:1 to 1:1

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Note

  • Figure 2.3 shows the timing relationship between the CHI clock, SCLK and SCLKEN, where SCLKEN asserts one CLK cycle before the rising edge of SCLK. It is important that the relationship between SCLK and SCLKEN is maintained.

  • The input signal SCLKEN exists in the multiprocessor if it is configured to include the CHI interface.

ACLKENS

ACP is a synchronous AXI slave interface that can operate at any integer multiple that is equal to or slower than the multiprocessor clock, CLK, using the ACLKENS signal. For example, the CLK to ACLKS frequency ratio can be 1:1, 2:1, or 3:1, where ACLKS is the AXI slave clock. ACLKENS asserts one CLK cycle before the rising edge of ACLKS. The CLK to ACLKS frequency ratio can be changed dynamically using ACLKENS.

Figure 2.4 shows a timing example of ACLKENS that changes the CLK to ACLKS frequency ratio from 3:1 to 1:1.

Figure 2.4. ACLKENS with CLK:ACLKS ratio changing from 3:1 to 1:1

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Note

Figure 2.4 shows the timing relationship between the ACP clock, ACLKS and ACLKENS, where ACLKENS asserts one CLK cycle before the rising edge of ACLKS. It is important that the relationship between ACLKS and ACLKENS is maintained.

PCLKENDBG

The Debug APB interface is an asynchronous interface that can operate at any integer multiple that is equal to or slower than the APB clock, PCLKDBG, using the PCLKENDBG signal. For example, the PCLKDBG to internal PCLKDBG frequency ratio can be 1:1, 2:1, or 3:1. PCLKENDBG asserts one PCLKDBG cycle before the rising edge of the internal PCLKDBG. The PCLKDBG to internal PCLKDBG frequency ratio can be changed dynamically using PCLKENDBG.

Figure 2.5 shows a timing example of PCLKENDBG that changes the PCLKDBG to internal PCLKDBG frequency ratio from 2:1 to 1:1.

Figure 2.5. PCLKENDBG with PCLKDBG:internal PCLKDBG ratio changing from 2:1 to 1:1

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ATCLKEN

The ATB interface is a synchronous interface that can operate at any integer multiple that is slower than the multiprocessor clock, CLK, using the ATCLKEN signal. For example, the CLK to ATCLK frequency ratio can be 2:1, 3:1, or 4:1, where ATCLK is the ATB bus clock. ATCLKEN asserts three CLK cycles before the rising edge of ATCLK. Three CLK cycles are required to allow propagation delay from the ATCLKEN input to the multiprocessor. The CLK to ATCLK frequency ratio can be changed dynamically using ATCLKEN.

Figure 2.6 shows a timing example of ATCLKEN where the CLK to ATCLK frequency ratio is 2:1.

Figure 2.6. ATCLKEN with CLK:ATCLK ratio at 2:1

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CNTCLKEN

The CNTVALUEB is a synchronous 64-bit binary encoded counter value that can operate at any integer multiple that is equal to or slower than the multiprocessor clock, CLK, using the CNTCLKEN signal. For example, you can set the CLK to CNTCLK frequency ratio to 1:1, 2:1, or 3:1, where CNTCLK is the system counter clock. CNTCLKEN asserts one CLK cycle prior to the rising edge of CNTCLK.

Figure 2.7 shows a timing example of CNTCLKEN where the CLK to CNTCLK frequency ratio is 2:1.

Figure 2.7. CNTCLKEN with CLK:CNTCLK ratio at 2:1

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CLKEN

This is the clock enable for all internal clocks in the multiprocessor that are derived from CLK. The CLKEN signal must be asserted at least one cycle before applying CLK to the multiprocessor.

When all the processors and L2 are in WFI low-power state, you can place the multiprocessor in a low-power state using the CLKEN input. Setting CLKEN LOW disables all of the internal clocks, excluding the asynchronous Debug APB PCLKDBG domain. See L2 Wait for Interrupt.

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