8.3.3. CPU interface System register descriptions

This section only describes registers whose implementation is specific to the Cortex-A57 MPCore multiprocessor. All other registers are described in the ARM® Generic Interrupt Controller Architecture Specification, GICv3. Table 8.4 provides cross-references to individual registers.

Active Priority Group0 Register

The ICC_AP0R0_EL1 characteristics are:

Purpose

Provides support for preserving and restoring state in power-management applications.

Usage constraints

Accessibility and constraints on this register are described in the ARM® Generic Interrupt Controller Architecture Specification, GICv3.

Configurations

Available if the GIC is implemented for System register mode.

Attributes

See the register summary in Table 8.4.

The multiprocessor implements the ICC_AP0R0_EL1 according to the recommendations described in the ARM® Generic Interrupt Controller Architecture Specification, GICv3.

Table 8.7 shows the Cortex-A57 MPCore multiprocessor ICC_AP0R0_EL1 implementation.

Table 8.7. Active Priority Group0 Register implementation

Number of group priority bitsPreemption levelsMinimum legal value of BPRActive Priority Group0 Registers implemented
5322ICC_AP0R0_EL1[31:0]

Active Priority Group1 Register

The ICC_AP1R0_EL1 characteristics are:

Purpose

Provides support for preserving and restoring state in power-management applications.

Usage constraints

This register is Banked to provide Secure and Non-secure copies. This ensures that Non-secure accesses do not interfere with Secure operation. Accessibility and constraints on this register are described in the ARM® Generic Interrupt Controller Architecture Specification, GICv3.

Configurations

Available if the GIC is implemented for System register mode.

Attributes

See the register summary in Table 8.4.

The multiprocessor implements the ICC_AP1R0_EL1 according to the recommendations described in the ARM® Generic Interrupt Controller Architecture Specification, GICv3.

Table 8.8 shows the Cortex-A57 MPCore multiprocessor ICC_AP1R0_EL1 implementation.

Table 8.8. Active Priority Group1 Register implementation

Number of group priority bitsPreemption levelsMinimum legal value of Secure BPRMinimum legal value of Non-secure BPRActive Priority Group1 Registers implemented
53223ICC_AP1R0_EL1[31:0]

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