10.11.2.  ROM table register summary

Table 10.30 shows the offsets from the physical base address of the ROM table.

Table 10.30. ROM table registers

OffsetNameTypeDescription
0x000ROMENTRY0ROProcessor 0 Debug, see ROM entry registers
0x004ROMENTRY1ROProcessor 0 CTI, see ROM entry registers
0x008ROMENTRY2ROProcessor 0 PMU, see ROM entry registers
0x00CROMENTRY3ROProcessor 0 ETM, see ROM entry registers
0x010ROMENTRY4ROProcessor 1 Debug, see ROM entry registers
0x014ROMENTRY5ROProcessor 1 CTI, see ROM entry registers
0x018ROMENTRY6ROProcessor 1 PMU, see ROM entry registers
0x01CROMENTRY7ROProcessor 1 ETM, see ROM entry registers
0x020ROMENTRY8ROProcessor 2 Debug, see ROM entry registers
0x024ROMENTRY9ROProcessor 2 CTI, see ROM entry registers
0x028ROMENTRY10ROProcessor 2 PMU, see ROM entry registers
0x02CROMENTRY11ROProcessor 2 ETM, see ROM entry registers
0x030ROMENTRY12ROProcessor 3 Debug, see ROM entry registers
0x034ROMENTRY13ROProcessor 3 CTI, see ROM entry registers
0x038ROMENTRY14ROProcessor 3 PMU, see ROM entry registers
0x03CROMENTRY15ROProcessor 3 ETM, see ROM entry registers
0x040-0xFCC-ROReserved, res0
0xFD0ROMPIDR4ROROM table Debug Peripheral Identification Register 4
0xFD4ROMPIDR5ROROM table Debug Peripheral Identification Register 5-7
0xFD8ROMPIDR6RO
0xFDCROMPIDR7RO
0xFE0ROMPIDR0ROROM table Debug Peripheral Identification Register 0
0xFE4ROMPIDR1ROROM table Debug Peripheral Identification Register 1
0xFE8ROMPIDR2ROROM table Debug Peripheral Identification Register 2
0xFECROMPIDR3ROROM table Debug Peripheral Identification Register 3
0xFF0ROMCIDR0ROROM table Debug Component Identification Register 0
0xFF4ROMCIDR1ROROM table Debug Component Identification Register 1
0xFF8ROMCIDR2ROROM table Debug Component Identification Register 2
0xFFCROMCIDR3ROROM table Debug Component Identification Register 3

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