10.11.5. ROM table Debug Component Identification Registers

There are four read-only ROM table Debug Component Identification Registers, Component ID0 through Component ID3. Table 10.39 shows these registers.

Table 10.39. Summary of the ROM table Debug component Identification registers

RegisterValueOffset
ROMCIDR00x0D0xFF0
ROMCIDR10x100xFF4
ROMCIDR20x050xFF8
ROMCIDR30xB10xFFC

The ROM table Debug Component Identification Registers identify Debug as an ARM Debug Interface v5 component. The ROM table Component ID registers are:

ROM table Debug Component Identification Register 0

The ROMCIDR0 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The ROMCIDR0 is in the Debug power domain.

Attributes

See the register summary in Table 10.30.

Figure 10.30 shows the ROMCIDR0 bit assignments.

Figure 10.30. ROMCIDR0 bit assignments

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Table 10.40 shows the ROMCIDR0 bit assignments.

Table 10.40. ROMCIDR0 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:0]PRMBL_0
0x0D

Preamble byte 0


ROM table Debug Component Identification Register 1

The ROMCIDR1 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The ROMCIDR1 is in the Debug power domain.

Attributes

See the register summary in Table 10.30.

Figure 10.31 shows the ROMCIDR1 bit assignments.

Figure 10.31. ROMCIDR1 bit assignments

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Table 10.41 shows the ROMCIDR1 bit assignments.

Table 10.41. ROMCIDR1 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]CLASS
0x1

Component Class. For a ROM table.

[3:0]PRMBL_1
0x0

Preamble.


ROM table Debug Component Identification Register 2

The ROMCIDR2 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The ROMCIDR2 is in the Debug power domain.

Attributes

See the register summary in Table 10.30.

Figure 10.32 shows the ROMCIDR2 bit assignments.

Figure 10.32. ROMCIDR2 bit assignments

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Table 10.42 shows the ROMCIDR2 bit assignments.

Table 10.42. ROMCIDR2 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:0]PRMBL_2
0x05

Preamble byte 2


ROM table Debug Component Identification Register 3

The ROMCIDR3 characteristics are:

Purpose

Provides information to identify an external debug component.

Usage constraints

Accessible through the internal memory-mapped interface and the external debug interface. The access conditions are:

OffDLKOSLKEDADSLKDefault
-----RO

Table 10.1 describes the access conditions.

Configurations

The ROMCIDR3 is in the Debug power domain.

Attributes

See the register summary in Table 10.30.

Figure 10.33 shows the ROMCIDR3 bit assignments.

Figure 10.33. ROMCIDR3 bit assignments

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Table 10.43 shows the ROMCIDR3 bit assignments.

Table 10.43. ROMCIDR3 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:0]PRMBL_3
0xB1

Preamble byte 3


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