11.7.13. PMU Component Identification Registers

There are four read-only PMU Component Identification Registers, Component ID0 through Component ID3. Table 11.19 shows these registers.

Table 11.19. Summary of the PMU Component Identification Registers

RegisterValueOffset
PMCIDR00x0D0xFF0
PMCIDR10x900xFF4
PMCIDR20x050xFF8
PMCIDR30xB10xFFC

The PMU Component Identification Registers identify Performance Monitors as ARM PMUv3 architecture. The PMU Component ID registers are:

PMU Component Identification Register 0

The PMCIDR0 characteristics are:

Purpose

Provides information to identify a Performance Monitors component.

Usage constraints

The PMCIDR0 can be accessed through the internal memory-mapped interface and the external debug interface.

The accessibility to the PMCIDR0 by condition code is:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 11.1 describes the condition codes.

Configurations

The PMCIDR0 is in the Debug power domain.

Attributes

See the register summary in Table 11.7.

Figure 11.14 shows the PMCIDR0 bit assignments.

Figure 11.14. PMCIDR0 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 11.20 shows the PMCIDR0 bit assignments.

Table 11.20. PMCIDR0 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:0]PRMBL_0
0x0D

Preamble byte 0


The PMCIDR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF0.

PMU Component Identification Register 1

The PMCIDR1 characteristics are:

Purpose

Provides information to identify a Performance Monitors component.

Usage constraints

The PMCIDR1 can be accessed through the internal memory-mapped interface and the external debug interface.

The accessibility to the PMCIDR1 by condition code is:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 11.1 describes the condition codes.

Configurations

The PMCIDR1 is in the Debug power domain.

Attributes

See the register summary in Table 11.7.

Figure 11.15 shows the PMCIDR1 bit assignments.

Figure 11.15. PMCIDR1 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 11.21 shows the PMCIDR1 bit assignments.

Table 11.21. PMCIDR1 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:4]CLASS
0x9

Debug component

[3:0]PRMBL_1
0x0

Preamble


The PMCIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF4.

PMU Component Identification Register 2

The PMCIDR2 characteristics are:

Purpose

Provides information to identify a Performance Monitors component.

Usage constraints

The PMCIDR2 can be accessed through the internal memory-mapped interface and the external debug interface.

The accessibility to the PMCIDR2 by condition code is:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 11.1 describes the condition codes.

Configurations

The PMCIDR2 is in the Debug power domain.

Attributes

See the register summary in Table 11.7.

Figure 11.16 shows the PMCIDR2 bit assignments.

Figure 11.16. PMCIDR2 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 11.22 shows the PMCIDR2 bit assignments.

Table 11.22. PMCIDR2 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:0]PRMBL_2
0x05

Preamble byte 2


The PMCIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF8.

PMU Component Identification Register 3

The PMCIDR3 characteristics are:

Purpose

Provides information to identify a Performance Monitors component.

Usage constraints

The PMCIDR3 can be accessed through the internal memory-mapped interface and the external debug interface.

The accessibility to the PMCIDR3 by condition code is:

OffDLKOSLKEPMADSLKDefault
----RORO

Table 11.1 describes the condition codes.

Configurations

The PMCIDR3 is in the Debug power domain.

Attributes

See the register summary in Table 11.7.

Figure 11.17 shows the PMCIDR3 bit assignments.

Figure 11.17. PMCIDR3 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 11.23 shows the PMCIDR3 bit assignments.

Table 11.23. PMCIDR3 bit assignments

BitsNameFunction
[31:8]-

Reserved, res0

[7:0]PRMBL_3
0xB1

Preamble byte 3


The PMCIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFFC.

Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0488D
Non-ConfidentialID012914